1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #if TRANSFER_LIST 23 #include <lib/transfer_list.h> 24 #endif 25 #ifdef SPD_opteed 26 #include <lib/optee_utils.h> 27 #endif 28 #include <lib/utils.h> 29 #include <plat/arm/common/plat_arm.h> 30 #include <plat/common/platform.h> 31 32 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 34 35 /* Base address of fw_config received from BL1 */ 36 static uintptr_t config_base; 37 38 /* 39 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 40 * for `meminfo_t` data structure and fw_configs passed from BL1. 41 */ 42 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 43 44 /* Weak definitions may be overridden in specific ARM standard platform */ 45 #pragma weak bl2_early_platform_setup2 46 #pragma weak bl2_platform_setup 47 #pragma weak bl2_plat_arch_setup 48 #pragma weak bl2_plat_sec_mem_layout 49 50 #if ENABLE_RME 51 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 52 bl2_tzram_layout.total_base, \ 53 bl2_tzram_layout.total_size, \ 54 MT_MEMORY | MT_RW | MT_ROOT) 55 #else 56 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 57 bl2_tzram_layout.total_base, \ 58 bl2_tzram_layout.total_size, \ 59 MT_MEMORY | MT_RW | MT_SECURE) 60 #endif /* ENABLE_RME */ 61 62 #pragma weak arm_bl2_plat_handle_post_image_load 63 64 static struct transfer_list_header *secure_tl __unused; 65 static struct transfer_list_header *ns_tl __unused; 66 67 /******************************************************************************* 68 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 69 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 70 * Copy it to a safe location before its reclaimed by later BL2 functionality. 71 ******************************************************************************/ 72 void arm_bl2_early_platform_setup(uintptr_t fw_config, 73 struct meminfo *mem_layout) 74 { 75 int __maybe_unused ret; 76 77 /* Initialize the console to provide early debug support */ 78 arm_console_boot_init(); 79 80 /* Setup the BL2 memory layout */ 81 bl2_tzram_layout = *mem_layout; 82 83 config_base = fw_config; 84 85 /* Initialise the IO layer and register platform IO devices */ 86 plat_arm_io_setup(); 87 88 /* Load partition table */ 89 #if ARM_GPT_SUPPORT 90 ret = gpt_partition_init(); 91 if (ret != 0) { 92 ERROR("GPT partition initialisation failed!\n"); 93 panic(); 94 } 95 96 #endif /* ARM_GPT_SUPPORT */ 97 } 98 99 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 100 { 101 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 102 103 generic_delay_timer_init(); 104 } 105 106 /* 107 * Perform BL2 preload setup. Currently we initialise the dynamic 108 * configuration here. 109 */ 110 void bl2_plat_preload_setup(void) 111 { 112 #if TRANSFER_LIST 113 secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE, 114 PLAT_ARM_FW_HANDOFF_SIZE); 115 if (secure_tl == NULL) { 116 ERROR("Initialisation of secure transfer list failed!\n"); 117 panic(); 118 } 119 120 arm_transfer_list_dyn_cfg_init(secure_tl); 121 #else 122 arm_bl2_dyn_cfg_init(); 123 #endif 124 125 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 126 /* Always use the FIP from bank 0 */ 127 arm_set_fip_addr(0U); 128 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 129 } 130 131 /* 132 * Perform ARM standard platform setup. 133 */ 134 void arm_bl2_platform_setup(void) 135 { 136 #if !ENABLE_RME 137 /* Initialize the secure environment */ 138 plat_arm_security_setup(); 139 #endif 140 141 #if defined(PLAT_ARM_MEM_PROT_ADDR) 142 arm_nor_psci_do_static_mem_protect(); 143 #endif 144 145 #if TRANSFER_LIST 146 ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, 147 PLAT_ARM_FW_HANDOFF_SIZE); 148 149 if (ns_tl == NULL) { 150 ERROR("Non-secure transfer list initialisation failed!"); 151 panic(); 152 } 153 #endif 154 } 155 156 void bl2_platform_setup(void) 157 { 158 arm_bl2_platform_setup(); 159 } 160 161 /******************************************************************************* 162 * Perform the very early platform specific architectural setup here. 163 * When RME is enabled the secure environment is initialised before 164 * initialising and enabling Granule Protection. 165 * This function initialises the MMU in a quick and dirty way. 166 ******************************************************************************/ 167 void arm_bl2_plat_arch_setup(void) 168 { 169 #if USE_COHERENT_MEM 170 /* Ensure ARM platforms don't use coherent memory in BL2. */ 171 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 172 #endif 173 174 const mmap_region_t bl_regions[] = { 175 MAP_BL2_TOTAL, 176 ARM_MAP_BL_RO, 177 #if USE_ROMLIB 178 ARM_MAP_ROMLIB_CODE, 179 ARM_MAP_ROMLIB_DATA, 180 #endif 181 ARM_MAP_BL_CONFIG_REGION, 182 #if ENABLE_RME 183 ARM_MAP_L0_GPT_REGION, 184 #endif 185 {0} 186 }; 187 188 #if ENABLE_RME 189 /* Initialise the secure environment */ 190 plat_arm_security_setup(); 191 #endif 192 setup_page_tables(bl_regions, plat_arm_get_mmap()); 193 194 #ifdef __aarch64__ 195 #if ENABLE_RME 196 /* BL2 runs in EL3 when RME enabled. */ 197 assert(get_armv9_2_feat_rme_support() != 0U); 198 enable_mmu_el3(0); 199 200 /* Initialise and enable granule protection after MMU. */ 201 arm_gpt_setup(); 202 #else 203 enable_mmu_el1(0); 204 #endif 205 #else 206 enable_mmu_svc_mon(0); 207 #endif 208 209 arm_setup_romlib(); 210 } 211 212 void bl2_plat_arch_setup(void) 213 { 214 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 215 216 arm_bl2_plat_arch_setup(); 217 218 /* Fill the properties struct with the info from the config dtb */ 219 fconf_populate("FW_CONFIG", config_base); 220 221 /* TB_FW_CONFIG was also loaded by BL1 */ 222 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 223 assert(tb_fw_config_info != NULL); 224 225 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 226 } 227 228 int arm_bl2_handle_post_image_load(unsigned int image_id) 229 { 230 int err = 0; 231 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 232 #ifdef SPD_opteed 233 bl_mem_params_node_t *pager_mem_params = NULL; 234 bl_mem_params_node_t *paged_mem_params = NULL; 235 #endif 236 assert(bl_mem_params != NULL); 237 238 switch (image_id) { 239 #ifdef __aarch64__ 240 case BL32_IMAGE_ID: 241 #ifdef SPD_opteed 242 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 243 assert(pager_mem_params); 244 245 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 246 assert(paged_mem_params); 247 248 err = parse_optee_header(&bl_mem_params->ep_info, 249 &pager_mem_params->image_info, 250 &paged_mem_params->image_info); 251 if (err != 0) { 252 WARN("OPTEE header parse error.\n"); 253 } 254 #endif 255 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 256 break; 257 #endif 258 259 case BL33_IMAGE_ID: 260 /* BL33 expects to receive the primary CPU MPID (through r0) */ 261 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 262 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 263 break; 264 265 #ifdef SCP_BL2_BASE 266 case SCP_BL2_IMAGE_ID: 267 /* The subsequent handling of SCP_BL2 is platform specific */ 268 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 269 if (err) { 270 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 271 } 272 break; 273 #endif 274 default: 275 /* Do nothing in default case */ 276 break; 277 } 278 279 return err; 280 } 281 282 /******************************************************************************* 283 * This function can be used by the platforms to update/use image 284 * information for given `image_id`. 285 ******************************************************************************/ 286 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 287 { 288 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 289 /* For Secure Partitions we don't need post processing */ 290 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 291 (image_id < MAX_NUMBER_IDS)) { 292 return 0; 293 } 294 #endif 295 296 #if TRANSFER_LIST 297 if (image_id == HW_CONFIG_ID) { 298 arm_transfer_list_copy_hw_config(secure_tl, ns_tl); 299 } 300 #endif /* TRANSFER_LIST */ 301 302 return arm_bl2_handle_post_image_load(image_id); 303 } 304 305 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node) 306 { 307 assert(transfer_list_set_handoff_args( 308 secure_tl, &next_param_node->ep_info) != NULL); 309 310 arm_transfer_list_populate_ep_info(next_param_node, secure_tl, ns_tl); 311 } 312