1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <desc_image_load.h> 14 #include <plat_arm.h> 15 #include <platform_def.h> 16 #include <platform.h> 17 #include <string.h> 18 #include <utils.h> 19 20 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 21 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 22 23 /* Weak definitions may be overridden in specific ARM standard platform */ 24 #pragma weak bl2_early_platform_setup 25 #pragma weak bl2_platform_setup 26 #pragma weak bl2_plat_arch_setup 27 #pragma weak bl2_plat_sec_mem_layout 28 29 #if LOAD_IMAGE_V2 30 31 #pragma weak bl2_plat_handle_post_image_load 32 33 #else /* LOAD_IMAGE_V2 */ 34 35 /******************************************************************************* 36 * This structure represents the superset of information that is passed to 37 * BL31, e.g. while passing control to it from BL2, bl31_params 38 * and other platform specific params 39 ******************************************************************************/ 40 typedef struct bl2_to_bl31_params_mem { 41 bl31_params_t bl31_params; 42 image_info_t bl31_image_info; 43 image_info_t bl32_image_info; 44 image_info_t bl33_image_info; 45 entry_point_info_t bl33_ep_info; 46 entry_point_info_t bl32_ep_info; 47 entry_point_info_t bl31_ep_info; 48 } bl2_to_bl31_params_mem_t; 49 50 51 static bl2_to_bl31_params_mem_t bl31_params_mem; 52 53 54 /* Weak definitions may be overridden in specific ARM standard platform */ 55 #pragma weak bl2_plat_get_bl31_params 56 #pragma weak bl2_plat_get_bl31_ep_info 57 #pragma weak bl2_plat_flush_bl31_params 58 #pragma weak bl2_plat_set_bl31_ep_info 59 #pragma weak bl2_plat_get_scp_bl2_meminfo 60 #pragma weak bl2_plat_get_bl32_meminfo 61 #pragma weak bl2_plat_set_bl32_ep_info 62 #pragma weak bl2_plat_get_bl33_meminfo 63 #pragma weak bl2_plat_set_bl33_ep_info 64 65 #if ARM_BL31_IN_DRAM 66 meminfo_t *bl2_plat_sec_mem_layout(void) 67 { 68 static meminfo_t bl2_dram_layout 69 __aligned(CACHE_WRITEBACK_GRANULE) = { 70 .total_base = BL31_BASE, 71 .total_size = (ARM_AP_TZC_DRAM1_BASE + 72 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 73 .free_base = BL31_BASE, 74 .free_size = (ARM_AP_TZC_DRAM1_BASE + 75 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 76 }; 77 78 return &bl2_dram_layout; 79 } 80 #else 81 meminfo_t *bl2_plat_sec_mem_layout(void) 82 { 83 return &bl2_tzram_layout; 84 } 85 #endif /* ARM_BL31_IN_DRAM */ 86 87 /******************************************************************************* 88 * This function assigns a pointer to the memory that the platform has kept 89 * aside to pass platform specific and trusted firmware related information 90 * to BL31. This memory is allocated by allocating memory to 91 * bl2_to_bl31_params_mem_t structure which is a superset of all the 92 * structure whose information is passed to BL31 93 * NOTE: This function should be called only once and should be done 94 * before generating params to BL31 95 ******************************************************************************/ 96 bl31_params_t *bl2_plat_get_bl31_params(void) 97 { 98 bl31_params_t *bl2_to_bl31_params; 99 100 /* 101 * Initialise the memory for all the arguments that needs to 102 * be passed to BL31 103 */ 104 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 105 106 /* Assign memory for TF related information */ 107 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 108 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 109 110 /* Fill BL31 related information */ 111 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 112 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 113 VERSION_1, 0); 114 115 /* Fill BL32 related information if it exists */ 116 #ifdef BL32_BASE 117 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 118 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 119 VERSION_1, 0); 120 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 121 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 122 VERSION_1, 0); 123 #endif /* BL32_BASE */ 124 125 /* Fill BL33 related information */ 126 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 127 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 128 PARAM_EP, VERSION_1, 0); 129 130 /* BL33 expects to receive the primary CPU MPID (through x0) */ 131 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 132 133 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 134 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 135 VERSION_1, 0); 136 137 return bl2_to_bl31_params; 138 } 139 140 /* Flush the TF params and the TF plat params */ 141 void bl2_plat_flush_bl31_params(void) 142 { 143 flush_dcache_range((unsigned long)&bl31_params_mem, 144 sizeof(bl2_to_bl31_params_mem_t)); 145 } 146 147 /******************************************************************************* 148 * This function returns a pointer to the shared memory that the platform 149 * has kept to point to entry point information of BL31 to BL2 150 ******************************************************************************/ 151 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 152 { 153 #if DEBUG 154 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; 155 #endif 156 157 return &bl31_params_mem.bl31_ep_info; 158 } 159 #endif /* LOAD_IMAGE_V2 */ 160 161 /******************************************************************************* 162 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 163 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 164 * Copy it to a safe location before its reclaimed by later BL2 functionality. 165 ******************************************************************************/ 166 void arm_bl2_early_platform_setup(meminfo_t *mem_layout) 167 { 168 /* Initialize the console to provide early debug support */ 169 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 170 ARM_CONSOLE_BAUDRATE); 171 172 /* Setup the BL2 memory layout */ 173 bl2_tzram_layout = *mem_layout; 174 175 /* Initialise the IO layer and register platform IO devices */ 176 plat_arm_io_setup(); 177 } 178 179 void bl2_early_platform_setup(meminfo_t *mem_layout) 180 { 181 arm_bl2_early_platform_setup(mem_layout); 182 } 183 184 /* 185 * Perform ARM standard platform setup. 186 */ 187 void arm_bl2_platform_setup(void) 188 { 189 /* Initialize the secure environment */ 190 plat_arm_security_setup(); 191 } 192 193 void bl2_platform_setup(void) 194 { 195 arm_bl2_platform_setup(); 196 } 197 198 /******************************************************************************* 199 * Perform the very early platform specific architectural setup here. At the 200 * moment this is only initializes the mmu in a quick and dirty way. 201 ******************************************************************************/ 202 void arm_bl2_plat_arch_setup(void) 203 { 204 arm_setup_page_tables(bl2_tzram_layout.total_base, 205 bl2_tzram_layout.total_size, 206 BL_CODE_BASE, 207 BL_CODE_END, 208 BL_RO_DATA_BASE, 209 BL_RO_DATA_END 210 #if USE_COHERENT_MEM 211 , BL_COHERENT_RAM_BASE, 212 BL_COHERENT_RAM_END 213 #endif 214 ); 215 216 #ifdef AARCH32 217 enable_mmu_secure(0); 218 #else 219 enable_mmu_el1(0); 220 #endif 221 } 222 223 void bl2_plat_arch_setup(void) 224 { 225 arm_bl2_plat_arch_setup(); 226 } 227 228 #if LOAD_IMAGE_V2 229 int arm_bl2_handle_post_image_load(unsigned int image_id) 230 { 231 int err = 0; 232 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 233 assert(bl_mem_params); 234 235 switch (image_id) { 236 #ifdef AARCH64 237 case BL32_IMAGE_ID: 238 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 239 break; 240 #endif 241 242 case BL33_IMAGE_ID: 243 /* BL33 expects to receive the primary CPU MPID (through r0) */ 244 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 245 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 246 break; 247 248 #ifdef SCP_BL2_BASE 249 case SCP_BL2_IMAGE_ID: 250 /* The subsequent handling of SCP_BL2 is platform specific */ 251 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 252 if (err) { 253 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 254 } 255 break; 256 #endif 257 } 258 259 return err; 260 } 261 262 /******************************************************************************* 263 * This function can be used by the platforms to update/use image 264 * information for given `image_id`. 265 ******************************************************************************/ 266 int bl2_plat_handle_post_image_load(unsigned int image_id) 267 { 268 return arm_bl2_handle_post_image_load(image_id); 269 } 270 271 #else /* LOAD_IMAGE_V2 */ 272 273 /******************************************************************************* 274 * Populate the extents of memory available for loading SCP_BL2 (if used), 275 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 276 ******************************************************************************/ 277 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 278 { 279 *scp_bl2_meminfo = bl2_tzram_layout; 280 } 281 282 /******************************************************************************* 283 * Before calling this function BL31 is loaded in memory and its entrypoint 284 * is set by load_image. This is a placeholder for the platform to change 285 * the entrypoint of BL31 and set SPSR and security state. 286 * On ARM standard platforms we only set the security state of the entrypoint 287 ******************************************************************************/ 288 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 289 entry_point_info_t *bl31_ep_info) 290 { 291 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 292 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 293 DISABLE_ALL_EXCEPTIONS); 294 } 295 296 297 /******************************************************************************* 298 * Before calling this function BL32 is loaded in memory and its entrypoint 299 * is set by load_image. This is a placeholder for the platform to change 300 * the entrypoint of BL32 and set SPSR and security state. 301 * On ARM standard platforms we only set the security state of the entrypoint 302 ******************************************************************************/ 303 #ifdef BL32_BASE 304 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 305 entry_point_info_t *bl32_ep_info) 306 { 307 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 308 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 309 } 310 311 /******************************************************************************* 312 * Populate the extents of memory available for loading BL32 313 ******************************************************************************/ 314 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 315 { 316 /* 317 * Populate the extents of memory available for loading BL32. 318 */ 319 bl32_meminfo->total_base = BL32_BASE; 320 bl32_meminfo->free_base = BL32_BASE; 321 bl32_meminfo->total_size = 322 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 323 bl32_meminfo->free_size = 324 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 325 } 326 #endif /* BL32_BASE */ 327 328 /******************************************************************************* 329 * Before calling this function BL33 is loaded in memory and its entrypoint 330 * is set by load_image. This is a placeholder for the platform to change 331 * the entrypoint of BL33 and set SPSR and security state. 332 * On ARM standard platforms we only set the security state of the entrypoint 333 ******************************************************************************/ 334 void bl2_plat_set_bl33_ep_info(image_info_t *image, 335 entry_point_info_t *bl33_ep_info) 336 { 337 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 338 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 339 } 340 341 /******************************************************************************* 342 * Populate the extents of memory available for loading BL33 343 ******************************************************************************/ 344 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 345 { 346 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 347 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 348 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 349 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 350 } 351 352 #endif /* LOAD_IMAGE_V2 */ 353