1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <desc_image_load.h> 14 #ifdef SPD_opteed 15 #include <optee_utils.h> 16 #endif 17 #include <plat_arm.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <string.h> 21 #include <utils.h> 22 23 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 24 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 25 26 /* Weak definitions may be overridden in specific ARM standard platform */ 27 #pragma weak bl2_early_platform_setup 28 #pragma weak bl2_platform_setup 29 #pragma weak bl2_plat_arch_setup 30 #pragma weak bl2_plat_sec_mem_layout 31 32 #if LOAD_IMAGE_V2 33 34 #pragma weak bl2_plat_handle_post_image_load 35 36 #else /* LOAD_IMAGE_V2 */ 37 38 /******************************************************************************* 39 * This structure represents the superset of information that is passed to 40 * BL31, e.g. while passing control to it from BL2, bl31_params 41 * and other platform specific params 42 ******************************************************************************/ 43 typedef struct bl2_to_bl31_params_mem { 44 bl31_params_t bl31_params; 45 image_info_t bl31_image_info; 46 image_info_t bl32_image_info; 47 image_info_t bl33_image_info; 48 entry_point_info_t bl33_ep_info; 49 entry_point_info_t bl32_ep_info; 50 entry_point_info_t bl31_ep_info; 51 } bl2_to_bl31_params_mem_t; 52 53 54 static bl2_to_bl31_params_mem_t bl31_params_mem; 55 56 57 /* Weak definitions may be overridden in specific ARM standard platform */ 58 #pragma weak bl2_plat_get_bl31_params 59 #pragma weak bl2_plat_get_bl31_ep_info 60 #pragma weak bl2_plat_flush_bl31_params 61 #pragma weak bl2_plat_set_bl31_ep_info 62 #pragma weak bl2_plat_get_scp_bl2_meminfo 63 #pragma weak bl2_plat_get_bl32_meminfo 64 #pragma weak bl2_plat_set_bl32_ep_info 65 #pragma weak bl2_plat_get_bl33_meminfo 66 #pragma weak bl2_plat_set_bl33_ep_info 67 68 #if ARM_BL31_IN_DRAM 69 meminfo_t *bl2_plat_sec_mem_layout(void) 70 { 71 static meminfo_t bl2_dram_layout 72 __aligned(CACHE_WRITEBACK_GRANULE) = { 73 .total_base = BL31_BASE, 74 .total_size = (ARM_AP_TZC_DRAM1_BASE + 75 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 76 .free_base = BL31_BASE, 77 .free_size = (ARM_AP_TZC_DRAM1_BASE + 78 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 79 }; 80 81 return &bl2_dram_layout; 82 } 83 #else 84 meminfo_t *bl2_plat_sec_mem_layout(void) 85 { 86 return &bl2_tzram_layout; 87 } 88 #endif /* ARM_BL31_IN_DRAM */ 89 90 /******************************************************************************* 91 * This function assigns a pointer to the memory that the platform has kept 92 * aside to pass platform specific and trusted firmware related information 93 * to BL31. This memory is allocated by allocating memory to 94 * bl2_to_bl31_params_mem_t structure which is a superset of all the 95 * structure whose information is passed to BL31 96 * NOTE: This function should be called only once and should be done 97 * before generating params to BL31 98 ******************************************************************************/ 99 bl31_params_t *bl2_plat_get_bl31_params(void) 100 { 101 bl31_params_t *bl2_to_bl31_params; 102 103 /* 104 * Initialise the memory for all the arguments that needs to 105 * be passed to BL31 106 */ 107 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 108 109 /* Assign memory for TF related information */ 110 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 111 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 112 113 /* Fill BL31 related information */ 114 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 115 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 116 VERSION_1, 0); 117 118 /* Fill BL32 related information if it exists */ 119 #ifdef BL32_BASE 120 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 121 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 122 VERSION_1, 0); 123 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 124 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 125 VERSION_1, 0); 126 #endif /* BL32_BASE */ 127 128 /* Fill BL33 related information */ 129 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 130 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 131 PARAM_EP, VERSION_1, 0); 132 133 /* BL33 expects to receive the primary CPU MPID (through x0) */ 134 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 135 136 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 137 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 138 VERSION_1, 0); 139 140 return bl2_to_bl31_params; 141 } 142 143 /* Flush the TF params and the TF plat params */ 144 void bl2_plat_flush_bl31_params(void) 145 { 146 flush_dcache_range((unsigned long)&bl31_params_mem, 147 sizeof(bl2_to_bl31_params_mem_t)); 148 } 149 150 /******************************************************************************* 151 * This function returns a pointer to the shared memory that the platform 152 * has kept to point to entry point information of BL31 to BL2 153 ******************************************************************************/ 154 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 155 { 156 #if DEBUG 157 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; 158 #endif 159 160 return &bl31_params_mem.bl31_ep_info; 161 } 162 #endif /* LOAD_IMAGE_V2 */ 163 164 /******************************************************************************* 165 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 166 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 167 * Copy it to a safe location before its reclaimed by later BL2 functionality. 168 ******************************************************************************/ 169 void arm_bl2_early_platform_setup(meminfo_t *mem_layout) 170 { 171 /* Initialize the console to provide early debug support */ 172 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 173 ARM_CONSOLE_BAUDRATE); 174 175 /* Setup the BL2 memory layout */ 176 bl2_tzram_layout = *mem_layout; 177 178 /* Initialise the IO layer and register platform IO devices */ 179 plat_arm_io_setup(); 180 } 181 182 void bl2_early_platform_setup(meminfo_t *mem_layout) 183 { 184 arm_bl2_early_platform_setup(mem_layout); 185 } 186 187 /* 188 * Perform ARM standard platform setup. 189 */ 190 void arm_bl2_platform_setup(void) 191 { 192 /* Initialize the secure environment */ 193 plat_arm_security_setup(); 194 } 195 196 void bl2_platform_setup(void) 197 { 198 arm_bl2_platform_setup(); 199 } 200 201 /******************************************************************************* 202 * Perform the very early platform specific architectural setup here. At the 203 * moment this is only initializes the mmu in a quick and dirty way. 204 ******************************************************************************/ 205 void arm_bl2_plat_arch_setup(void) 206 { 207 arm_setup_page_tables(bl2_tzram_layout.total_base, 208 bl2_tzram_layout.total_size, 209 BL_CODE_BASE, 210 BL_CODE_END, 211 BL_RO_DATA_BASE, 212 BL_RO_DATA_END 213 #if USE_COHERENT_MEM 214 , BL_COHERENT_RAM_BASE, 215 BL_COHERENT_RAM_END 216 #endif 217 ); 218 219 #ifdef AARCH32 220 enable_mmu_secure(0); 221 #else 222 enable_mmu_el1(0); 223 #endif 224 } 225 226 void bl2_plat_arch_setup(void) 227 { 228 arm_bl2_plat_arch_setup(); 229 } 230 231 #if LOAD_IMAGE_V2 232 int arm_bl2_handle_post_image_load(unsigned int image_id) 233 { 234 int err = 0; 235 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 236 #ifdef SPD_opteed 237 bl_mem_params_node_t *pager_mem_params = NULL; 238 bl_mem_params_node_t *paged_mem_params = NULL; 239 #endif 240 assert(bl_mem_params); 241 242 switch (image_id) { 243 #ifdef AARCH64 244 case BL32_IMAGE_ID: 245 #ifdef SPD_opteed 246 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 247 assert(pager_mem_params); 248 249 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 250 assert(paged_mem_params); 251 252 err = parse_optee_header(&bl_mem_params->ep_info, 253 &pager_mem_params->image_info, 254 &paged_mem_params->image_info); 255 if (err != 0) { 256 WARN("OPTEE header parse error.\n"); 257 } 258 #endif 259 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 260 break; 261 #endif 262 263 case BL33_IMAGE_ID: 264 /* BL33 expects to receive the primary CPU MPID (through r0) */ 265 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 266 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 267 break; 268 269 #ifdef SCP_BL2_BASE 270 case SCP_BL2_IMAGE_ID: 271 /* The subsequent handling of SCP_BL2 is platform specific */ 272 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 273 if (err) { 274 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 275 } 276 break; 277 #endif 278 } 279 280 return err; 281 } 282 283 /******************************************************************************* 284 * This function can be used by the platforms to update/use image 285 * information for given `image_id`. 286 ******************************************************************************/ 287 int bl2_plat_handle_post_image_load(unsigned int image_id) 288 { 289 return arm_bl2_handle_post_image_load(image_id); 290 } 291 292 #else /* LOAD_IMAGE_V2 */ 293 294 /******************************************************************************* 295 * Populate the extents of memory available for loading SCP_BL2 (if used), 296 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 297 ******************************************************************************/ 298 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 299 { 300 *scp_bl2_meminfo = bl2_tzram_layout; 301 } 302 303 /******************************************************************************* 304 * Before calling this function BL31 is loaded in memory and its entrypoint 305 * is set by load_image. This is a placeholder for the platform to change 306 * the entrypoint of BL31 and set SPSR and security state. 307 * On ARM standard platforms we only set the security state of the entrypoint 308 ******************************************************************************/ 309 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 310 entry_point_info_t *bl31_ep_info) 311 { 312 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 313 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 314 DISABLE_ALL_EXCEPTIONS); 315 } 316 317 318 /******************************************************************************* 319 * Before calling this function BL32 is loaded in memory and its entrypoint 320 * is set by load_image. This is a placeholder for the platform to change 321 * the entrypoint of BL32 and set SPSR and security state. 322 * On ARM standard platforms we only set the security state of the entrypoint 323 ******************************************************************************/ 324 #ifdef BL32_BASE 325 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 326 entry_point_info_t *bl32_ep_info) 327 { 328 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 329 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 330 } 331 332 /******************************************************************************* 333 * Populate the extents of memory available for loading BL32 334 ******************************************************************************/ 335 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 336 { 337 /* 338 * Populate the extents of memory available for loading BL32. 339 */ 340 bl32_meminfo->total_base = BL32_BASE; 341 bl32_meminfo->free_base = BL32_BASE; 342 bl32_meminfo->total_size = 343 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 344 bl32_meminfo->free_size = 345 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 346 } 347 #endif /* BL32_BASE */ 348 349 /******************************************************************************* 350 * Before calling this function BL33 is loaded in memory and its entrypoint 351 * is set by load_image. This is a placeholder for the platform to change 352 * the entrypoint of BL33 and set SPSR and security state. 353 * On ARM standard platforms we only set the security state of the entrypoint 354 ******************************************************************************/ 355 void bl2_plat_set_bl33_ep_info(image_info_t *image, 356 entry_point_info_t *bl33_ep_info) 357 { 358 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 359 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 360 } 361 362 /******************************************************************************* 363 * Populate the extents of memory available for loading BL33 364 ******************************************************************************/ 365 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 366 { 367 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 368 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 369 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 370 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 371 } 372 373 #endif /* LOAD_IMAGE_V2 */ 374