1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_def.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <platform_def.h> 36 #include <plat_arm.h> 37 #include <string.h> 38 39 #if USE_COHERENT_MEM 40 /* 41 * The next 2 constants identify the extents of the coherent memory region. 42 * These addresses are used by the MMU setup code and therefore they must be 43 * page-aligned. It is the responsibility of the linker script to ensure that 44 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 45 * page-aligned addresses. 46 */ 47 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 48 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 49 #endif 50 51 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 52 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 53 54 55 /******************************************************************************* 56 * This structure represents the superset of information that is passed to 57 * BL31, e.g. while passing control to it from BL2, bl31_params 58 * and other platform specific params 59 ******************************************************************************/ 60 typedef struct bl2_to_bl31_params_mem { 61 bl31_params_t bl31_params; 62 image_info_t bl31_image_info; 63 image_info_t bl32_image_info; 64 image_info_t bl33_image_info; 65 entry_point_info_t bl33_ep_info; 66 entry_point_info_t bl32_ep_info; 67 entry_point_info_t bl31_ep_info; 68 } bl2_to_bl31_params_mem_t; 69 70 71 static bl2_to_bl31_params_mem_t bl31_params_mem; 72 73 74 /* Weak definitions may be overridden in specific ARM standard platform */ 75 #pragma weak bl2_early_platform_setup 76 #pragma weak bl2_platform_setup 77 #pragma weak bl2_plat_arch_setup 78 #pragma weak bl2_plat_sec_mem_layout 79 #pragma weak bl2_plat_get_bl31_params 80 #pragma weak bl2_plat_get_bl31_ep_info 81 #pragma weak bl2_plat_flush_bl31_params 82 #pragma weak bl2_plat_set_bl31_ep_info 83 #pragma weak bl2_plat_get_scp_bl2_meminfo 84 #pragma weak bl2_plat_get_bl32_meminfo 85 #pragma weak bl2_plat_set_bl32_ep_info 86 #pragma weak bl2_plat_get_bl33_meminfo 87 #pragma weak bl2_plat_set_bl33_ep_info 88 89 #if ARM_BL31_IN_DRAM 90 meminfo_t *bl2_plat_sec_mem_layout(void) 91 { 92 static meminfo_t bl2_dram_layout 93 __aligned(CACHE_WRITEBACK_GRANULE) = { 94 .total_base = BL31_BASE, 95 .total_size = (ARM_AP_TZC_DRAM1_BASE + 96 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 97 .free_base = BL31_BASE, 98 .free_size = (ARM_AP_TZC_DRAM1_BASE + 99 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 100 }; 101 102 return &bl2_dram_layout; 103 } 104 #else 105 meminfo_t *bl2_plat_sec_mem_layout(void) 106 { 107 return &bl2_tzram_layout; 108 } 109 #endif 110 111 /******************************************************************************* 112 * This function assigns a pointer to the memory that the platform has kept 113 * aside to pass platform specific and trusted firmware related information 114 * to BL31. This memory is allocated by allocating memory to 115 * bl2_to_bl31_params_mem_t structure which is a superset of all the 116 * structure whose information is passed to BL31 117 * NOTE: This function should be called only once and should be done 118 * before generating params to BL31 119 ******************************************************************************/ 120 bl31_params_t *bl2_plat_get_bl31_params(void) 121 { 122 bl31_params_t *bl2_to_bl31_params; 123 124 /* 125 * Initialise the memory for all the arguments that needs to 126 * be passed to BL31 127 */ 128 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 129 130 /* Assign memory for TF related information */ 131 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 132 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 133 134 /* Fill BL31 related information */ 135 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 136 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 137 VERSION_1, 0); 138 139 /* Fill BL32 related information if it exists */ 140 #ifdef BL32_BASE 141 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 142 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 143 VERSION_1, 0); 144 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 145 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 146 VERSION_1, 0); 147 #endif /* BL32_BASE */ 148 149 /* Fill BL33 related information */ 150 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 151 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 152 PARAM_EP, VERSION_1, 0); 153 154 /* BL33 expects to receive the primary CPU MPID (through x0) */ 155 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 156 157 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 158 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 159 VERSION_1, 0); 160 161 return bl2_to_bl31_params; 162 } 163 164 /* Flush the TF params and the TF plat params */ 165 void bl2_plat_flush_bl31_params(void) 166 { 167 flush_dcache_range((unsigned long)&bl31_params_mem, 168 sizeof(bl2_to_bl31_params_mem_t)); 169 } 170 171 /******************************************************************************* 172 * This function returns a pointer to the shared memory that the platform 173 * has kept to point to entry point information of BL31 to BL2 174 ******************************************************************************/ 175 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 176 { 177 #if DEBUG 178 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; 179 #endif 180 181 return &bl31_params_mem.bl31_ep_info; 182 } 183 184 /******************************************************************************* 185 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 186 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 187 * Copy it to a safe location before its reclaimed by later BL2 functionality. 188 ******************************************************************************/ 189 void arm_bl2_early_platform_setup(meminfo_t *mem_layout) 190 { 191 /* Initialize the console to provide early debug support */ 192 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 193 ARM_CONSOLE_BAUDRATE); 194 195 /* Setup the BL2 memory layout */ 196 bl2_tzram_layout = *mem_layout; 197 198 /* Initialise the IO layer and register platform IO devices */ 199 plat_arm_io_setup(); 200 } 201 202 void bl2_early_platform_setup(meminfo_t *mem_layout) 203 { 204 arm_bl2_early_platform_setup(mem_layout); 205 } 206 207 /* 208 * Perform ARM standard platform setup. 209 */ 210 void arm_bl2_platform_setup(void) 211 { 212 /* Initialize the secure environment */ 213 plat_arm_security_setup(); 214 } 215 216 void bl2_platform_setup(void) 217 { 218 arm_bl2_platform_setup(); 219 } 220 221 /******************************************************************************* 222 * Perform the very early platform specific architectural setup here. At the 223 * moment this is only initializes the mmu in a quick and dirty way. 224 ******************************************************************************/ 225 void arm_bl2_plat_arch_setup(void) 226 { 227 arm_setup_page_tables(bl2_tzram_layout.total_base, 228 bl2_tzram_layout.total_size, 229 BL_CODE_BASE, 230 BL_CODE_LIMIT, 231 BL_RO_DATA_BASE, 232 BL_RO_DATA_LIMIT 233 #if USE_COHERENT_MEM 234 , BL2_COHERENT_RAM_BASE, 235 BL2_COHERENT_RAM_LIMIT 236 #endif 237 ); 238 enable_mmu_el1(0); 239 } 240 241 void bl2_plat_arch_setup(void) 242 { 243 arm_bl2_plat_arch_setup(); 244 } 245 246 /******************************************************************************* 247 * Populate the extents of memory available for loading SCP_BL2 (if used), 248 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 249 ******************************************************************************/ 250 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 251 { 252 *scp_bl2_meminfo = bl2_tzram_layout; 253 } 254 255 /******************************************************************************* 256 * Before calling this function BL31 is loaded in memory and its entrypoint 257 * is set by load_image. This is a placeholder for the platform to change 258 * the entrypoint of BL31 and set SPSR and security state. 259 * On ARM standard platforms we only set the security state of the entrypoint 260 ******************************************************************************/ 261 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 262 entry_point_info_t *bl31_ep_info) 263 { 264 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 265 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 266 DISABLE_ALL_EXCEPTIONS); 267 } 268 269 270 /******************************************************************************* 271 * Before calling this function BL32 is loaded in memory and its entrypoint 272 * is set by load_image. This is a placeholder for the platform to change 273 * the entrypoint of BL32 and set SPSR and security state. 274 * On ARM standard platforms we only set the security state of the entrypoint 275 ******************************************************************************/ 276 #ifdef BL32_BASE 277 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 278 entry_point_info_t *bl32_ep_info) 279 { 280 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 281 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 282 } 283 284 /******************************************************************************* 285 * Populate the extents of memory available for loading BL32 286 ******************************************************************************/ 287 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 288 { 289 /* 290 * Populate the extents of memory available for loading BL32. 291 */ 292 bl32_meminfo->total_base = BL32_BASE; 293 bl32_meminfo->free_base = BL32_BASE; 294 bl32_meminfo->total_size = 295 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 296 bl32_meminfo->free_size = 297 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 298 } 299 #endif /* BL32_BASE */ 300 301 /******************************************************************************* 302 * Before calling this function BL33 is loaded in memory and its entrypoint 303 * is set by load_image. This is a placeholder for the platform to change 304 * the entrypoint of BL33 and set SPSR and security state. 305 * On ARM standard platforms we only set the security state of the entrypoint 306 ******************************************************************************/ 307 void bl2_plat_set_bl33_ep_info(image_info_t *image, 308 entry_point_info_t *bl33_ep_info) 309 { 310 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 311 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 312 } 313 314 /******************************************************************************* 315 * Populate the extents of memory available for loading BL33 316 ******************************************************************************/ 317 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 318 { 319 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 320 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 321 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 322 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 323 } 324