1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_def.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <console.h> 36 #include <debug.h> 37 #include <desc_image_load.h> 38 #include <plat_arm.h> 39 #include <platform_def.h> 40 #include <string.h> 41 #include <utils.h> 42 43 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 44 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 45 46 /* Weak definitions may be overridden in specific ARM standard platform */ 47 #pragma weak bl2_early_platform_setup 48 #pragma weak bl2_platform_setup 49 #pragma weak bl2_plat_arch_setup 50 #pragma weak bl2_plat_sec_mem_layout 51 52 #if LOAD_IMAGE_V2 53 54 #pragma weak bl2_plat_handle_post_image_load 55 56 #else /* LOAD_IMAGE_V2 */ 57 58 /******************************************************************************* 59 * This structure represents the superset of information that is passed to 60 * BL31, e.g. while passing control to it from BL2, bl31_params 61 * and other platform specific params 62 ******************************************************************************/ 63 typedef struct bl2_to_bl31_params_mem { 64 bl31_params_t bl31_params; 65 image_info_t bl31_image_info; 66 image_info_t bl32_image_info; 67 image_info_t bl33_image_info; 68 entry_point_info_t bl33_ep_info; 69 entry_point_info_t bl32_ep_info; 70 entry_point_info_t bl31_ep_info; 71 } bl2_to_bl31_params_mem_t; 72 73 74 static bl2_to_bl31_params_mem_t bl31_params_mem; 75 76 77 /* Weak definitions may be overridden in specific ARM standard platform */ 78 #pragma weak bl2_plat_get_bl31_params 79 #pragma weak bl2_plat_get_bl31_ep_info 80 #pragma weak bl2_plat_flush_bl31_params 81 #pragma weak bl2_plat_set_bl31_ep_info 82 #pragma weak bl2_plat_get_scp_bl2_meminfo 83 #pragma weak bl2_plat_get_bl32_meminfo 84 #pragma weak bl2_plat_set_bl32_ep_info 85 #pragma weak bl2_plat_get_bl33_meminfo 86 #pragma weak bl2_plat_set_bl33_ep_info 87 88 #if ARM_BL31_IN_DRAM 89 meminfo_t *bl2_plat_sec_mem_layout(void) 90 { 91 static meminfo_t bl2_dram_layout 92 __aligned(CACHE_WRITEBACK_GRANULE) = { 93 .total_base = BL31_BASE, 94 .total_size = (ARM_AP_TZC_DRAM1_BASE + 95 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 96 .free_base = BL31_BASE, 97 .free_size = (ARM_AP_TZC_DRAM1_BASE + 98 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 99 }; 100 101 return &bl2_dram_layout; 102 } 103 #else 104 meminfo_t *bl2_plat_sec_mem_layout(void) 105 { 106 return &bl2_tzram_layout; 107 } 108 #endif /* ARM_BL31_IN_DRAM */ 109 110 /******************************************************************************* 111 * This function assigns a pointer to the memory that the platform has kept 112 * aside to pass platform specific and trusted firmware related information 113 * to BL31. This memory is allocated by allocating memory to 114 * bl2_to_bl31_params_mem_t structure which is a superset of all the 115 * structure whose information is passed to BL31 116 * NOTE: This function should be called only once and should be done 117 * before generating params to BL31 118 ******************************************************************************/ 119 bl31_params_t *bl2_plat_get_bl31_params(void) 120 { 121 bl31_params_t *bl2_to_bl31_params; 122 123 /* 124 * Initialise the memory for all the arguments that needs to 125 * be passed to BL31 126 */ 127 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 128 129 /* Assign memory for TF related information */ 130 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 131 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 132 133 /* Fill BL31 related information */ 134 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 135 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 136 VERSION_1, 0); 137 138 /* Fill BL32 related information if it exists */ 139 #ifdef BL32_BASE 140 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 141 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 142 VERSION_1, 0); 143 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 144 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 145 VERSION_1, 0); 146 #endif /* BL32_BASE */ 147 148 /* Fill BL33 related information */ 149 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 150 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 151 PARAM_EP, VERSION_1, 0); 152 153 /* BL33 expects to receive the primary CPU MPID (through x0) */ 154 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 155 156 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 157 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 158 VERSION_1, 0); 159 160 return bl2_to_bl31_params; 161 } 162 163 /* Flush the TF params and the TF plat params */ 164 void bl2_plat_flush_bl31_params(void) 165 { 166 flush_dcache_range((unsigned long)&bl31_params_mem, 167 sizeof(bl2_to_bl31_params_mem_t)); 168 } 169 170 /******************************************************************************* 171 * This function returns a pointer to the shared memory that the platform 172 * has kept to point to entry point information of BL31 to BL2 173 ******************************************************************************/ 174 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 175 { 176 #if DEBUG 177 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; 178 #endif 179 180 return &bl31_params_mem.bl31_ep_info; 181 } 182 #endif /* LOAD_IMAGE_V2 */ 183 184 /******************************************************************************* 185 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 186 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 187 * Copy it to a safe location before its reclaimed by later BL2 functionality. 188 ******************************************************************************/ 189 void arm_bl2_early_platform_setup(meminfo_t *mem_layout) 190 { 191 /* Initialize the console to provide early debug support */ 192 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 193 ARM_CONSOLE_BAUDRATE); 194 195 /* Setup the BL2 memory layout */ 196 bl2_tzram_layout = *mem_layout; 197 198 /* Initialise the IO layer and register platform IO devices */ 199 plat_arm_io_setup(); 200 } 201 202 void bl2_early_platform_setup(meminfo_t *mem_layout) 203 { 204 arm_bl2_early_platform_setup(mem_layout); 205 } 206 207 /* 208 * Perform ARM standard platform setup. 209 */ 210 void arm_bl2_platform_setup(void) 211 { 212 /* Initialize the secure environment */ 213 plat_arm_security_setup(); 214 } 215 216 void bl2_platform_setup(void) 217 { 218 arm_bl2_platform_setup(); 219 } 220 221 /******************************************************************************* 222 * Perform the very early platform specific architectural setup here. At the 223 * moment this is only initializes the mmu in a quick and dirty way. 224 ******************************************************************************/ 225 void arm_bl2_plat_arch_setup(void) 226 { 227 arm_setup_page_tables(bl2_tzram_layout.total_base, 228 bl2_tzram_layout.total_size, 229 BL_CODE_BASE, 230 BL_CODE_END, 231 BL_RO_DATA_BASE, 232 BL_RO_DATA_END 233 #if USE_COHERENT_MEM 234 , BL_COHERENT_RAM_BASE, 235 BL_COHERENT_RAM_END 236 #endif 237 ); 238 239 #ifdef AARCH32 240 enable_mmu_secure(0); 241 #else 242 enable_mmu_el1(0); 243 #endif 244 } 245 246 void bl2_plat_arch_setup(void) 247 { 248 arm_bl2_plat_arch_setup(); 249 } 250 251 #if LOAD_IMAGE_V2 252 /******************************************************************************* 253 * This function can be used by the platforms to update/use image 254 * information for given `image_id`. 255 ******************************************************************************/ 256 int bl2_plat_handle_post_image_load(unsigned int image_id) 257 { 258 int err = 0; 259 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 260 assert(bl_mem_params); 261 262 switch (image_id) { 263 #ifdef AARCH64 264 case BL32_IMAGE_ID: 265 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 266 break; 267 #endif 268 269 case BL33_IMAGE_ID: 270 /* BL33 expects to receive the primary CPU MPID (through r0) */ 271 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 272 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 273 break; 274 275 #ifdef SCP_BL2_BASE 276 case SCP_BL2_IMAGE_ID: 277 /* The subsequent handling of SCP_BL2 is platform specific */ 278 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 279 if (err) { 280 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 281 } 282 break; 283 #endif 284 } 285 286 return err; 287 } 288 289 #else /* LOAD_IMAGE_V2 */ 290 291 /******************************************************************************* 292 * Populate the extents of memory available for loading SCP_BL2 (if used), 293 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 294 ******************************************************************************/ 295 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 296 { 297 *scp_bl2_meminfo = bl2_tzram_layout; 298 } 299 300 /******************************************************************************* 301 * Before calling this function BL31 is loaded in memory and its entrypoint 302 * is set by load_image. This is a placeholder for the platform to change 303 * the entrypoint of BL31 and set SPSR and security state. 304 * On ARM standard platforms we only set the security state of the entrypoint 305 ******************************************************************************/ 306 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 307 entry_point_info_t *bl31_ep_info) 308 { 309 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 310 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 311 DISABLE_ALL_EXCEPTIONS); 312 } 313 314 315 /******************************************************************************* 316 * Before calling this function BL32 is loaded in memory and its entrypoint 317 * is set by load_image. This is a placeholder for the platform to change 318 * the entrypoint of BL32 and set SPSR and security state. 319 * On ARM standard platforms we only set the security state of the entrypoint 320 ******************************************************************************/ 321 #ifdef BL32_BASE 322 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 323 entry_point_info_t *bl32_ep_info) 324 { 325 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 326 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 327 } 328 329 /******************************************************************************* 330 * Populate the extents of memory available for loading BL32 331 ******************************************************************************/ 332 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 333 { 334 /* 335 * Populate the extents of memory available for loading BL32. 336 */ 337 bl32_meminfo->total_base = BL32_BASE; 338 bl32_meminfo->free_base = BL32_BASE; 339 bl32_meminfo->total_size = 340 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 341 bl32_meminfo->free_size = 342 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 343 } 344 #endif /* BL32_BASE */ 345 346 /******************************************************************************* 347 * Before calling this function BL33 is loaded in memory and its entrypoint 348 * is set by load_image. This is a placeholder for the platform to change 349 * the entrypoint of BL33 and set SPSR and security state. 350 * On ARM standard platforms we only set the security state of the entrypoint 351 ******************************************************************************/ 352 void bl2_plat_set_bl33_ep_info(image_info_t *image, 353 entry_point_info_t *bl33_ep_info) 354 { 355 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 356 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 357 } 358 359 /******************************************************************************* 360 * Populate the extents of memory available for loading BL33 361 ******************************************************************************/ 362 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 363 { 364 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 365 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 366 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 367 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 368 } 369 370 #endif /* LOAD_IMAGE_V2 */ 371