1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_def.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <platform_def.h> 36 #include <plat_arm.h> 37 #include <string.h> 38 39 40 /* 41 * The next 2 constants identify the extents of the code & RO data region. 42 * These addresses are used by the MMU setup code and therefore they must be 43 * page-aligned. It is the responsibility of the linker script to ensure that 44 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 45 */ 46 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 47 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 48 49 #if USE_COHERENT_MEM 50 /* 51 * The next 2 constants identify the extents of the coherent memory region. 52 * These addresses are used by the MMU setup code and therefore they must be 53 * page-aligned. It is the responsibility of the linker script to ensure that 54 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 55 * page-aligned addresses. 56 */ 57 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 58 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 59 #endif 60 61 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 62 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 63 64 65 /******************************************************************************* 66 * This structure represents the superset of information that is passed to 67 * BL31, e.g. while passing control to it from BL2, bl31_params 68 * and other platform specific params 69 ******************************************************************************/ 70 typedef struct bl2_to_bl31_params_mem { 71 bl31_params_t bl31_params; 72 image_info_t bl31_image_info; 73 image_info_t bl32_image_info; 74 image_info_t bl33_image_info; 75 entry_point_info_t bl33_ep_info; 76 entry_point_info_t bl32_ep_info; 77 entry_point_info_t bl31_ep_info; 78 } bl2_to_bl31_params_mem_t; 79 80 81 static bl2_to_bl31_params_mem_t bl31_params_mem; 82 83 84 /* Weak definitions may be overridden in specific ARM standard platform */ 85 #pragma weak bl2_early_platform_setup 86 #pragma weak bl2_platform_setup 87 #pragma weak bl2_plat_arch_setup 88 #pragma weak bl2_plat_sec_mem_layout 89 #pragma weak bl2_plat_get_bl31_params 90 #pragma weak bl2_plat_get_bl31_ep_info 91 #pragma weak bl2_plat_flush_bl31_params 92 #pragma weak bl2_plat_set_bl31_ep_info 93 #pragma weak bl2_plat_get_scp_bl2_meminfo 94 #pragma weak bl2_plat_get_bl32_meminfo 95 #pragma weak bl2_plat_set_bl32_ep_info 96 #pragma weak bl2_plat_get_bl33_meminfo 97 #pragma weak bl2_plat_set_bl33_ep_info 98 99 #if ARM_BL31_IN_DRAM 100 meminfo_t *bl2_plat_sec_mem_layout(void) 101 { 102 static meminfo_t bl2_dram_layout 103 __aligned(CACHE_WRITEBACK_GRANULE) = { 104 .total_base = BL31_BASE, 105 .total_size = (ARM_AP_TZC_DRAM1_BASE + 106 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 107 .free_base = BL31_BASE, 108 .free_size = (ARM_AP_TZC_DRAM1_BASE + 109 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 110 }; 111 112 return &bl2_dram_layout; 113 } 114 #else 115 meminfo_t *bl2_plat_sec_mem_layout(void) 116 { 117 return &bl2_tzram_layout; 118 } 119 #endif 120 121 /******************************************************************************* 122 * This function assigns a pointer to the memory that the platform has kept 123 * aside to pass platform specific and trusted firmware related information 124 * to BL31. This memory is allocated by allocating memory to 125 * bl2_to_bl31_params_mem_t structure which is a superset of all the 126 * structure whose information is passed to BL31 127 * NOTE: This function should be called only once and should be done 128 * before generating params to BL31 129 ******************************************************************************/ 130 bl31_params_t *bl2_plat_get_bl31_params(void) 131 { 132 bl31_params_t *bl2_to_bl31_params; 133 134 /* 135 * Initialise the memory for all the arguments that needs to 136 * be passed to BL31 137 */ 138 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 139 140 /* Assign memory for TF related information */ 141 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 142 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 143 144 /* Fill BL31 related information */ 145 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 146 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 147 VERSION_1, 0); 148 149 /* Fill BL32 related information if it exists */ 150 #if BL32_BASE 151 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 152 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 153 VERSION_1, 0); 154 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 155 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 156 VERSION_1, 0); 157 #endif 158 159 /* Fill BL33 related information */ 160 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 161 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 162 PARAM_EP, VERSION_1, 0); 163 164 /* BL33 expects to receive the primary CPU MPID (through x0) */ 165 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 166 167 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 168 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 169 VERSION_1, 0); 170 171 return bl2_to_bl31_params; 172 } 173 174 /* Flush the TF params and the TF plat params */ 175 void bl2_plat_flush_bl31_params(void) 176 { 177 flush_dcache_range((unsigned long)&bl31_params_mem, 178 sizeof(bl2_to_bl31_params_mem_t)); 179 } 180 181 /******************************************************************************* 182 * This function returns a pointer to the shared memory that the platform 183 * has kept to point to entry point information of BL31 to BL2 184 ******************************************************************************/ 185 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 186 { 187 #if DEBUG 188 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; 189 #endif 190 191 return &bl31_params_mem.bl31_ep_info; 192 } 193 194 /******************************************************************************* 195 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 196 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 197 * Copy it to a safe location before its reclaimed by later BL2 functionality. 198 ******************************************************************************/ 199 void arm_bl2_early_platform_setup(meminfo_t *mem_layout) 200 { 201 /* Initialize the console to provide early debug support */ 202 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 203 ARM_CONSOLE_BAUDRATE); 204 205 /* Setup the BL2 memory layout */ 206 bl2_tzram_layout = *mem_layout; 207 208 /* Initialise the IO layer and register platform IO devices */ 209 plat_arm_io_setup(); 210 } 211 212 void bl2_early_platform_setup(meminfo_t *mem_layout) 213 { 214 arm_bl2_early_platform_setup(mem_layout); 215 } 216 217 /* 218 * Perform ARM standard platform setup. 219 */ 220 void arm_bl2_platform_setup(void) 221 { 222 /* Initialize the secure environment */ 223 plat_arm_security_setup(); 224 } 225 226 void bl2_platform_setup(void) 227 { 228 arm_bl2_platform_setup(); 229 } 230 231 /******************************************************************************* 232 * Perform the very early platform specific architectural setup here. At the 233 * moment this is only initializes the mmu in a quick and dirty way. 234 ******************************************************************************/ 235 void arm_bl2_plat_arch_setup(void) 236 { 237 arm_configure_mmu_el1(bl2_tzram_layout.total_base, 238 bl2_tzram_layout.total_size, 239 BL2_RO_BASE, 240 BL2_RO_LIMIT 241 #if USE_COHERENT_MEM 242 , BL2_COHERENT_RAM_BASE, 243 BL2_COHERENT_RAM_LIMIT 244 #endif 245 ); 246 } 247 248 void bl2_plat_arch_setup(void) 249 { 250 arm_bl2_plat_arch_setup(); 251 } 252 253 /******************************************************************************* 254 * Populate the extents of memory available for loading SCP_BL2 (if used), 255 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 256 ******************************************************************************/ 257 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 258 { 259 *scp_bl2_meminfo = bl2_tzram_layout; 260 } 261 262 /******************************************************************************* 263 * Before calling this function BL31 is loaded in memory and its entrypoint 264 * is set by load_image. This is a placeholder for the platform to change 265 * the entrypoint of BL31 and set SPSR and security state. 266 * On ARM standard platforms we only set the security state of the entrypoint 267 ******************************************************************************/ 268 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 269 entry_point_info_t *bl31_ep_info) 270 { 271 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 272 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 273 DISABLE_ALL_EXCEPTIONS); 274 } 275 276 277 /******************************************************************************* 278 * Before calling this function BL32 is loaded in memory and its entrypoint 279 * is set by load_image. This is a placeholder for the platform to change 280 * the entrypoint of BL32 and set SPSR and security state. 281 * On ARM standard platforms we only set the security state of the entrypoint 282 ******************************************************************************/ 283 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 284 entry_point_info_t *bl32_ep_info) 285 { 286 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 287 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 288 } 289 290 /******************************************************************************* 291 * Before calling this function BL33 is loaded in memory and its entrypoint 292 * is set by load_image. This is a placeholder for the platform to change 293 * the entrypoint of BL33 and set SPSR and security state. 294 * On ARM standard platforms we only set the security state of the entrypoint 295 ******************************************************************************/ 296 void bl2_plat_set_bl33_ep_info(image_info_t *image, 297 entry_point_info_t *bl33_ep_info) 298 { 299 300 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 301 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 302 } 303 304 /******************************************************************************* 305 * Populate the extents of memory available for loading BL32 306 ******************************************************************************/ 307 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 308 { 309 /* 310 * Populate the extents of memory available for loading BL32. 311 */ 312 bl32_meminfo->total_base = BL32_BASE; 313 bl32_meminfo->free_base = BL32_BASE; 314 bl32_meminfo->total_size = 315 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 316 bl32_meminfo->free_size = 317 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 318 } 319 320 321 /******************************************************************************* 322 * Populate the extents of memory available for loading BL33 323 ******************************************************************************/ 324 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 325 { 326 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 327 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 328 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 329 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 330 } 331