1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/fconf/fconf.h> 18 #include <lib/fconf/fconf_dyn_cfg_getter.h> 19 #ifdef SPD_opteed 20 #include <lib/optee_utils.h> 21 #endif 22 #include <lib/utils.h> 23 #include <plat/arm/common/plat_arm.h> 24 #include <plat/common/platform.h> 25 26 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 28 29 /* 30 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 31 * for `meminfo_t` data structure and fw_configs passed from BL1. 32 */ 33 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 34 35 /* Weak definitions may be overridden in specific ARM standard platform */ 36 #pragma weak bl2_early_platform_setup2 37 #pragma weak bl2_platform_setup 38 #pragma weak bl2_plat_arch_setup 39 #pragma weak bl2_plat_sec_mem_layout 40 #if MEASURED_BOOT 41 #pragma weak bl2_plat_get_hash 42 #endif 43 44 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 45 bl2_tzram_layout.total_base, \ 46 bl2_tzram_layout.total_size, \ 47 MT_MEMORY | MT_RW | MT_SECURE) 48 49 50 #pragma weak arm_bl2_plat_handle_post_image_load 51 52 /******************************************************************************* 53 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 54 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 55 * Copy it to a safe location before its reclaimed by later BL2 functionality. 56 ******************************************************************************/ 57 void arm_bl2_early_platform_setup(uintptr_t fw_config, 58 struct meminfo *mem_layout) 59 { 60 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 61 /* Initialize the console to provide early debug support */ 62 arm_console_boot_init(); 63 64 /* Setup the BL2 memory layout */ 65 bl2_tzram_layout = *mem_layout; 66 67 /* Fill the properties struct with the info from the config dtb */ 68 fconf_populate("FW_CONFIG", fw_config); 69 70 /* TB_FW_CONFIG was also loaded by BL1 */ 71 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 72 assert(tb_fw_config_info != NULL); 73 74 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 75 76 /* Initialise the IO layer and register platform IO devices */ 77 plat_arm_io_setup(); 78 } 79 80 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 81 { 82 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 83 84 generic_delay_timer_init(); 85 } 86 87 /* 88 * Perform BL2 preload setup. Currently we initialise the dynamic 89 * configuration here. 90 */ 91 void bl2_plat_preload_setup(void) 92 { 93 arm_bl2_dyn_cfg_init(); 94 } 95 96 /* 97 * Perform ARM standard platform setup. 98 */ 99 void arm_bl2_platform_setup(void) 100 { 101 /* Initialize the secure environment */ 102 plat_arm_security_setup(); 103 104 #if defined(PLAT_ARM_MEM_PROT_ADDR) 105 arm_nor_psci_do_static_mem_protect(); 106 #endif 107 } 108 109 void bl2_platform_setup(void) 110 { 111 arm_bl2_platform_setup(); 112 } 113 114 /******************************************************************************* 115 * Perform the very early platform specific architectural setup here. At the 116 * moment this is only initializes the mmu in a quick and dirty way. 117 ******************************************************************************/ 118 void arm_bl2_plat_arch_setup(void) 119 { 120 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 121 /* 122 * Ensure ARM platforms don't use coherent memory in BL2 unless 123 * cryptocell integration is enabled. 124 */ 125 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 126 #endif 127 128 const mmap_region_t bl_regions[] = { 129 MAP_BL2_TOTAL, 130 ARM_MAP_BL_RO, 131 #if USE_ROMLIB 132 ARM_MAP_ROMLIB_CODE, 133 ARM_MAP_ROMLIB_DATA, 134 #endif 135 #if ARM_CRYPTOCELL_INTEG 136 ARM_MAP_BL_COHERENT_RAM, 137 #endif 138 {0} 139 }; 140 141 setup_page_tables(bl_regions, plat_arm_get_mmap()); 142 143 #ifdef __aarch64__ 144 enable_mmu_el1(0); 145 #else 146 enable_mmu_svc_mon(0); 147 #endif 148 149 arm_setup_romlib(); 150 } 151 152 void bl2_plat_arch_setup(void) 153 { 154 arm_bl2_plat_arch_setup(); 155 } 156 157 int arm_bl2_handle_post_image_load(unsigned int image_id) 158 { 159 int err = 0; 160 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 161 #ifdef SPD_opteed 162 bl_mem_params_node_t *pager_mem_params = NULL; 163 bl_mem_params_node_t *paged_mem_params = NULL; 164 #endif 165 assert(bl_mem_params != NULL); 166 167 switch (image_id) { 168 #ifdef __aarch64__ 169 case BL32_IMAGE_ID: 170 #ifdef SPD_opteed 171 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 172 assert(pager_mem_params); 173 174 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 175 assert(paged_mem_params); 176 177 err = parse_optee_header(&bl_mem_params->ep_info, 178 &pager_mem_params->image_info, 179 &paged_mem_params->image_info); 180 if (err != 0) { 181 WARN("OPTEE header parse error.\n"); 182 } 183 #endif 184 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 185 break; 186 #endif 187 188 case BL33_IMAGE_ID: 189 /* BL33 expects to receive the primary CPU MPID (through r0) */ 190 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 191 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 192 break; 193 194 #ifdef SCP_BL2_BASE 195 case SCP_BL2_IMAGE_ID: 196 /* The subsequent handling of SCP_BL2 is platform specific */ 197 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 198 if (err) { 199 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 200 } 201 break; 202 #endif 203 default: 204 /* Do nothing in default case */ 205 break; 206 } 207 208 return err; 209 } 210 211 /******************************************************************************* 212 * This function can be used by the platforms to update/use image 213 * information for given `image_id`. 214 ******************************************************************************/ 215 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 216 { 217 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 218 /* For Secure Partitions we don't need post processing */ 219 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 220 (image_id < MAX_NUMBER_IDS)) { 221 return 0; 222 } 223 #endif 224 return arm_bl2_handle_post_image_load(image_id); 225 } 226 227 int bl2_plat_handle_post_image_load(unsigned int image_id) 228 { 229 return arm_bl2_plat_handle_post_image_load(image_id); 230 } 231 232 #if MEASURED_BOOT 233 /* Read TCG_DIGEST_SIZE bytes of BL2 hash data */ 234 void bl2_plat_get_hash(void *data) 235 { 236 arm_bl2_get_hash(data); 237 } 238 #endif 239