1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/fconf/fconf.h> 18 #include <lib/fconf/fconf_dyn_cfg_getter.h> 19 #ifdef SPD_opteed 20 #include <lib/optee_utils.h> 21 #endif 22 #include <lib/utils.h> 23 #include <plat/arm/common/plat_arm.h> 24 #include <plat/common/platform.h> 25 26 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 28 29 /* Base address of fw_config received from BL1 */ 30 static uintptr_t config_base; 31 32 /* 33 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 34 * for `meminfo_t` data structure and fw_configs passed from BL1. 35 */ 36 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 37 38 /* Weak definitions may be overridden in specific ARM standard platform */ 39 #pragma weak bl2_early_platform_setup2 40 #pragma weak bl2_platform_setup 41 #pragma weak bl2_plat_arch_setup 42 #pragma weak bl2_plat_sec_mem_layout 43 #if MEASURED_BOOT 44 #pragma weak bl2_plat_get_hash 45 #endif 46 47 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 48 bl2_tzram_layout.total_base, \ 49 bl2_tzram_layout.total_size, \ 50 MT_MEMORY | MT_RW | MT_SECURE) 51 52 53 #pragma weak arm_bl2_plat_handle_post_image_load 54 55 /******************************************************************************* 56 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 57 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 58 * Copy it to a safe location before its reclaimed by later BL2 functionality. 59 ******************************************************************************/ 60 void arm_bl2_early_platform_setup(uintptr_t fw_config, 61 struct meminfo *mem_layout) 62 { 63 /* Initialize the console to provide early debug support */ 64 arm_console_boot_init(); 65 66 /* Setup the BL2 memory layout */ 67 bl2_tzram_layout = *mem_layout; 68 69 config_base = fw_config; 70 71 /* Initialise the IO layer and register platform IO devices */ 72 plat_arm_io_setup(); 73 } 74 75 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 76 { 77 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 78 79 generic_delay_timer_init(); 80 } 81 82 /* 83 * Perform BL2 preload setup. Currently we initialise the dynamic 84 * configuration here. 85 */ 86 void bl2_plat_preload_setup(void) 87 { 88 arm_bl2_dyn_cfg_init(); 89 } 90 91 /* 92 * Perform ARM standard platform setup. 93 */ 94 void arm_bl2_platform_setup(void) 95 { 96 /* Initialize the secure environment */ 97 plat_arm_security_setup(); 98 99 #if defined(PLAT_ARM_MEM_PROT_ADDR) 100 arm_nor_psci_do_static_mem_protect(); 101 #endif 102 } 103 104 void bl2_platform_setup(void) 105 { 106 arm_bl2_platform_setup(); 107 } 108 109 /******************************************************************************* 110 * Perform the very early platform specific architectural setup here. At the 111 * moment this is only initializes the mmu in a quick and dirty way. 112 ******************************************************************************/ 113 void arm_bl2_plat_arch_setup(void) 114 { 115 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 116 /* 117 * Ensure ARM platforms don't use coherent memory in BL2 unless 118 * cryptocell integration is enabled. 119 */ 120 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 121 #endif 122 123 const mmap_region_t bl_regions[] = { 124 MAP_BL2_TOTAL, 125 ARM_MAP_BL_RO, 126 #if USE_ROMLIB 127 ARM_MAP_ROMLIB_CODE, 128 ARM_MAP_ROMLIB_DATA, 129 #endif 130 #if ARM_CRYPTOCELL_INTEG 131 ARM_MAP_BL_COHERENT_RAM, 132 #endif 133 ARM_MAP_BL_CONFIG_REGION, 134 {0} 135 }; 136 137 setup_page_tables(bl_regions, plat_arm_get_mmap()); 138 139 #ifdef __aarch64__ 140 enable_mmu_el1(0); 141 #else 142 enable_mmu_svc_mon(0); 143 #endif 144 145 arm_setup_romlib(); 146 } 147 148 void bl2_plat_arch_setup(void) 149 { 150 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 151 152 arm_bl2_plat_arch_setup(); 153 154 /* Fill the properties struct with the info from the config dtb */ 155 fconf_populate("FW_CONFIG", config_base); 156 157 /* TB_FW_CONFIG was also loaded by BL1 */ 158 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 159 assert(tb_fw_config_info != NULL); 160 161 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 162 } 163 164 int arm_bl2_handle_post_image_load(unsigned int image_id) 165 { 166 int err = 0; 167 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 168 #ifdef SPD_opteed 169 bl_mem_params_node_t *pager_mem_params = NULL; 170 bl_mem_params_node_t *paged_mem_params = NULL; 171 #endif 172 assert(bl_mem_params != NULL); 173 174 switch (image_id) { 175 #ifdef __aarch64__ 176 case BL32_IMAGE_ID: 177 #ifdef SPD_opteed 178 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 179 assert(pager_mem_params); 180 181 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 182 assert(paged_mem_params); 183 184 err = parse_optee_header(&bl_mem_params->ep_info, 185 &pager_mem_params->image_info, 186 &paged_mem_params->image_info); 187 if (err != 0) { 188 WARN("OPTEE header parse error.\n"); 189 } 190 #endif 191 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 192 break; 193 #endif 194 195 case BL33_IMAGE_ID: 196 /* BL33 expects to receive the primary CPU MPID (through r0) */ 197 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 198 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 199 break; 200 201 #ifdef SCP_BL2_BASE 202 case SCP_BL2_IMAGE_ID: 203 /* The subsequent handling of SCP_BL2 is platform specific */ 204 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 205 if (err) { 206 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 207 } 208 break; 209 #endif 210 default: 211 /* Do nothing in default case */ 212 break; 213 } 214 215 return err; 216 } 217 218 /******************************************************************************* 219 * This function can be used by the platforms to update/use image 220 * information for given `image_id`. 221 ******************************************************************************/ 222 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 223 { 224 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 225 /* For Secure Partitions we don't need post processing */ 226 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 227 (image_id < MAX_NUMBER_IDS)) { 228 return 0; 229 } 230 #endif 231 return arm_bl2_handle_post_image_load(image_id); 232 } 233 234 int bl2_plat_handle_post_image_load(unsigned int image_id) 235 { 236 return arm_bl2_plat_handle_post_image_load(image_id); 237 } 238 239 #if MEASURED_BOOT 240 /* Read TCG_DIGEST_SIZE bytes of BL2 hash data */ 241 void bl2_plat_get_hash(void *data) 242 { 243 arm_bl2_get_hash(data); 244 } 245 #endif 246