1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/fconf/fconf.h> 18 #include <lib/fconf/fconf_dyn_cfg_getter.h> 19 #ifdef SPD_opteed 20 #include <lib/optee_utils.h> 21 #endif 22 #include <lib/utils.h> 23 #include <plat/arm/common/plat_arm.h> 24 #include <plat/common/platform.h> 25 26 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 28 29 /* 30 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 31 * for `meminfo_t` data structure and fw_configs passed from BL1. 32 */ 33 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 34 35 /* Weak definitions may be overridden in specific ARM standard platform */ 36 #pragma weak bl2_early_platform_setup2 37 #pragma weak bl2_platform_setup 38 #pragma weak bl2_plat_arch_setup 39 #pragma weak bl2_plat_sec_mem_layout 40 41 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 42 bl2_tzram_layout.total_base, \ 43 bl2_tzram_layout.total_size, \ 44 MT_MEMORY | MT_RW | MT_SECURE) 45 46 47 #pragma weak arm_bl2_plat_handle_post_image_load 48 49 /******************************************************************************* 50 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 51 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 52 * Copy it to a safe location before its reclaimed by later BL2 functionality. 53 ******************************************************************************/ 54 void arm_bl2_early_platform_setup(uintptr_t fw_config, 55 struct meminfo *mem_layout) 56 { 57 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 58 /* Initialize the console to provide early debug support */ 59 arm_console_boot_init(); 60 61 /* Setup the BL2 memory layout */ 62 bl2_tzram_layout = *mem_layout; 63 64 /* Fill the properties struct with the info from the config dtb */ 65 fconf_populate("FW_CONFIG", fw_config); 66 67 /* TB_FW_CONFIG was also loaded by BL1 */ 68 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 69 assert(tb_fw_config_info != NULL); 70 71 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 72 73 /* Initialise the IO layer and register platform IO devices */ 74 plat_arm_io_setup(); 75 } 76 77 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 78 { 79 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 80 81 generic_delay_timer_init(); 82 } 83 84 /* 85 * Perform BL2 preload setup. Currently we initialise the dynamic 86 * configuration here. 87 */ 88 void bl2_plat_preload_setup(void) 89 { 90 arm_bl2_dyn_cfg_init(); 91 } 92 93 /* 94 * Perform ARM standard platform setup. 95 */ 96 void arm_bl2_platform_setup(void) 97 { 98 /* Initialize the secure environment */ 99 plat_arm_security_setup(); 100 101 #if defined(PLAT_ARM_MEM_PROT_ADDR) 102 arm_nor_psci_do_static_mem_protect(); 103 #endif 104 } 105 106 void bl2_platform_setup(void) 107 { 108 arm_bl2_platform_setup(); 109 } 110 111 /******************************************************************************* 112 * Perform the very early platform specific architectural setup here. At the 113 * moment this is only initializes the mmu in a quick and dirty way. 114 ******************************************************************************/ 115 void arm_bl2_plat_arch_setup(void) 116 { 117 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 118 /* 119 * Ensure ARM platforms don't use coherent memory in BL2 unless 120 * cryptocell integration is enabled. 121 */ 122 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 123 #endif 124 125 const mmap_region_t bl_regions[] = { 126 MAP_BL2_TOTAL, 127 ARM_MAP_BL_RO, 128 #if USE_ROMLIB 129 ARM_MAP_ROMLIB_CODE, 130 ARM_MAP_ROMLIB_DATA, 131 #endif 132 #if ARM_CRYPTOCELL_INTEG 133 ARM_MAP_BL_COHERENT_RAM, 134 #endif 135 {0} 136 }; 137 138 setup_page_tables(bl_regions, plat_arm_get_mmap()); 139 140 #ifdef __aarch64__ 141 enable_mmu_el1(0); 142 #else 143 enable_mmu_svc_mon(0); 144 #endif 145 146 arm_setup_romlib(); 147 } 148 149 void bl2_plat_arch_setup(void) 150 { 151 arm_bl2_plat_arch_setup(); 152 } 153 154 int arm_bl2_handle_post_image_load(unsigned int image_id) 155 { 156 int err = 0; 157 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 158 #ifdef SPD_opteed 159 bl_mem_params_node_t *pager_mem_params = NULL; 160 bl_mem_params_node_t *paged_mem_params = NULL; 161 #endif 162 assert(bl_mem_params != NULL); 163 164 switch (image_id) { 165 #ifdef __aarch64__ 166 case BL32_IMAGE_ID: 167 #ifdef SPD_opteed 168 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 169 assert(pager_mem_params); 170 171 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 172 assert(paged_mem_params); 173 174 err = parse_optee_header(&bl_mem_params->ep_info, 175 &pager_mem_params->image_info, 176 &paged_mem_params->image_info); 177 if (err != 0) { 178 WARN("OPTEE header parse error.\n"); 179 } 180 #endif 181 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 182 break; 183 #endif 184 185 case BL33_IMAGE_ID: 186 /* BL33 expects to receive the primary CPU MPID (through r0) */ 187 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 188 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 189 break; 190 191 #ifdef SCP_BL2_BASE 192 case SCP_BL2_IMAGE_ID: 193 /* The subsequent handling of SCP_BL2 is platform specific */ 194 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 195 if (err) { 196 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 197 } 198 break; 199 #endif 200 default: 201 /* Do nothing in default case */ 202 break; 203 } 204 205 return err; 206 } 207 208 /******************************************************************************* 209 * This function can be used by the platforms to update/use image 210 * information for given `image_id`. 211 ******************************************************************************/ 212 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 213 { 214 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 215 /* For Secure Partitions we don't need post processing */ 216 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 217 (image_id < MAX_NUMBER_IDS)) { 218 return 0; 219 } 220 #endif 221 return arm_bl2_handle_post_image_load(image_id); 222 } 223 224 int bl2_plat_handle_post_image_load(unsigned int image_id) 225 { 226 return arm_bl2_plat_handle_post_image_load(image_id); 227 } 228