1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/fconf/fconf.h> 18 #ifdef SPD_opteed 19 #include <lib/optee_utils.h> 20 #endif 21 #include <lib/utils.h> 22 #include <plat/arm/common/plat_arm.h> 23 #include <plat/common/platform.h> 24 25 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 26 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 27 28 /* 29 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 30 * for `meminfo_t` data structure and fw_configs passed from BL1. 31 */ 32 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 33 34 /* Weak definitions may be overridden in specific ARM standard platform */ 35 #pragma weak bl2_early_platform_setup2 36 #pragma weak bl2_platform_setup 37 #pragma weak bl2_plat_arch_setup 38 #pragma weak bl2_plat_sec_mem_layout 39 40 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 41 bl2_tzram_layout.total_base, \ 42 bl2_tzram_layout.total_size, \ 43 MT_MEMORY | MT_RW | MT_SECURE) 44 45 46 #pragma weak arm_bl2_plat_handle_post_image_load 47 48 /******************************************************************************* 49 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 50 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 51 * Copy it to a safe location before its reclaimed by later BL2 functionality. 52 ******************************************************************************/ 53 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, 54 struct meminfo *mem_layout) 55 { 56 /* Initialize the console to provide early debug support */ 57 arm_console_boot_init(); 58 59 /* Setup the BL2 memory layout */ 60 bl2_tzram_layout = *mem_layout; 61 62 /* Fill the properties struct with the info from the config dtb */ 63 if (tb_fw_config != 0U) { 64 fconf_populate("TB_FW", tb_fw_config); 65 } 66 67 /* Initialise the IO layer and register platform IO devices */ 68 plat_arm_io_setup(); 69 } 70 71 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 72 { 73 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 74 75 generic_delay_timer_init(); 76 } 77 78 /* 79 * Perform BL2 preload setup. Currently we initialise the dynamic 80 * configuration here. 81 */ 82 void bl2_plat_preload_setup(void) 83 { 84 arm_bl2_dyn_cfg_init(); 85 } 86 87 /* 88 * Perform ARM standard platform setup. 89 */ 90 void arm_bl2_platform_setup(void) 91 { 92 /* Initialize the secure environment */ 93 plat_arm_security_setup(); 94 95 #if defined(PLAT_ARM_MEM_PROT_ADDR) 96 arm_nor_psci_do_static_mem_protect(); 97 #endif 98 } 99 100 void bl2_platform_setup(void) 101 { 102 arm_bl2_platform_setup(); 103 } 104 105 /******************************************************************************* 106 * Perform the very early platform specific architectural setup here. At the 107 * moment this is only initializes the mmu in a quick and dirty way. 108 ******************************************************************************/ 109 void arm_bl2_plat_arch_setup(void) 110 { 111 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 112 /* 113 * Ensure ARM platforms don't use coherent memory in BL2 unless 114 * cryptocell integration is enabled. 115 */ 116 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 117 #endif 118 119 const mmap_region_t bl_regions[] = { 120 MAP_BL2_TOTAL, 121 ARM_MAP_BL_RO, 122 #if USE_ROMLIB 123 ARM_MAP_ROMLIB_CODE, 124 ARM_MAP_ROMLIB_DATA, 125 #endif 126 #if ARM_CRYPTOCELL_INTEG 127 ARM_MAP_BL_COHERENT_RAM, 128 #endif 129 {0} 130 }; 131 132 setup_page_tables(bl_regions, plat_arm_get_mmap()); 133 134 #ifdef __aarch64__ 135 enable_mmu_el1(0); 136 #else 137 enable_mmu_svc_mon(0); 138 #endif 139 140 arm_setup_romlib(); 141 } 142 143 void bl2_plat_arch_setup(void) 144 { 145 arm_bl2_plat_arch_setup(); 146 } 147 148 int arm_bl2_handle_post_image_load(unsigned int image_id) 149 { 150 int err = 0; 151 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 152 #ifdef SPD_opteed 153 bl_mem_params_node_t *pager_mem_params = NULL; 154 bl_mem_params_node_t *paged_mem_params = NULL; 155 #endif 156 assert(bl_mem_params != NULL); 157 158 switch (image_id) { 159 #ifdef __aarch64__ 160 case BL32_IMAGE_ID: 161 #ifdef SPD_opteed 162 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 163 assert(pager_mem_params); 164 165 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 166 assert(paged_mem_params); 167 168 err = parse_optee_header(&bl_mem_params->ep_info, 169 &pager_mem_params->image_info, 170 &paged_mem_params->image_info); 171 if (err != 0) { 172 WARN("OPTEE header parse error.\n"); 173 } 174 #endif 175 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 176 break; 177 #endif 178 179 case BL33_IMAGE_ID: 180 /* BL33 expects to receive the primary CPU MPID (through r0) */ 181 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 182 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 183 break; 184 185 #ifdef SCP_BL2_BASE 186 case SCP_BL2_IMAGE_ID: 187 /* The subsequent handling of SCP_BL2 is platform specific */ 188 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 189 if (err) { 190 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 191 } 192 break; 193 #endif 194 default: 195 /* Do nothing in default case */ 196 break; 197 } 198 199 return err; 200 } 201 202 /******************************************************************************* 203 * This function can be used by the platforms to update/use image 204 * information for given `image_id`. 205 ******************************************************************************/ 206 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 207 { 208 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 209 /* For Secure Partitions we don't need post processing */ 210 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 211 (image_id < MAX_NUMBER_IDS)) { 212 return 0; 213 } 214 #endif 215 return arm_bl2_handle_post_image_load(image_id); 216 } 217 218 int bl2_plat_handle_post_image_load(unsigned int image_id) 219 { 220 return arm_bl2_plat_handle_post_image_load(image_id); 221 } 222