1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <generic_delay_timer.h> 14 #ifdef SPD_opteed 15 #include <optee_utils.h> 16 #endif 17 #include <plat_arm.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <string.h> 21 #include <utils.h> 22 23 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 24 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 25 26 /* 27 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 28 * for `meminfo_t` data structure and fw_configs passed from BL1. 29 */ 30 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 31 32 /* Weak definitions may be overridden in specific ARM standard platform */ 33 #pragma weak bl2_early_platform_setup2 34 #pragma weak bl2_platform_setup 35 #pragma weak bl2_plat_arch_setup 36 #pragma weak bl2_plat_sec_mem_layout 37 38 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 39 bl2_tzram_layout.total_base, \ 40 bl2_tzram_layout.total_size, \ 41 MT_MEMORY | MT_RW | MT_SECURE) 42 43 #if LOAD_IMAGE_V2 44 45 #pragma weak bl2_plat_handle_post_image_load 46 47 #else /* LOAD_IMAGE_V2 */ 48 49 /******************************************************************************* 50 * This structure represents the superset of information that is passed to 51 * BL31, e.g. while passing control to it from BL2, bl31_params 52 * and other platform specific params 53 ******************************************************************************/ 54 typedef struct bl2_to_bl31_params_mem { 55 bl31_params_t bl31_params; 56 image_info_t bl31_image_info; 57 image_info_t bl32_image_info; 58 image_info_t bl33_image_info; 59 entry_point_info_t bl33_ep_info; 60 entry_point_info_t bl32_ep_info; 61 entry_point_info_t bl31_ep_info; 62 } bl2_to_bl31_params_mem_t; 63 64 65 static bl2_to_bl31_params_mem_t bl31_params_mem; 66 67 68 /* Weak definitions may be overridden in specific ARM standard platform */ 69 #pragma weak bl2_plat_get_bl31_params 70 #pragma weak bl2_plat_get_bl31_ep_info 71 #pragma weak bl2_plat_flush_bl31_params 72 #pragma weak bl2_plat_set_bl31_ep_info 73 #pragma weak bl2_plat_get_scp_bl2_meminfo 74 #pragma weak bl2_plat_get_bl32_meminfo 75 #pragma weak bl2_plat_set_bl32_ep_info 76 #pragma weak bl2_plat_get_bl33_meminfo 77 #pragma weak bl2_plat_set_bl33_ep_info 78 79 #if ARM_BL31_IN_DRAM 80 meminfo_t *bl2_plat_sec_mem_layout(void) 81 { 82 static meminfo_t bl2_dram_layout 83 __aligned(CACHE_WRITEBACK_GRANULE) = { 84 .total_base = BL31_BASE, 85 .total_size = (ARM_AP_TZC_DRAM1_BASE + 86 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 87 .free_base = BL31_BASE, 88 .free_size = (ARM_AP_TZC_DRAM1_BASE + 89 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 90 }; 91 92 return &bl2_dram_layout; 93 } 94 #else 95 meminfo_t *bl2_plat_sec_mem_layout(void) 96 { 97 return &bl2_tzram_layout; 98 } 99 #endif /* ARM_BL31_IN_DRAM */ 100 101 /******************************************************************************* 102 * This function assigns a pointer to the memory that the platform has kept 103 * aside to pass platform specific and trusted firmware related information 104 * to BL31. This memory is allocated by allocating memory to 105 * bl2_to_bl31_params_mem_t structure which is a superset of all the 106 * structure whose information is passed to BL31 107 * NOTE: This function should be called only once and should be done 108 * before generating params to BL31 109 ******************************************************************************/ 110 bl31_params_t *bl2_plat_get_bl31_params(void) 111 { 112 bl31_params_t *bl2_to_bl31_params; 113 114 /* 115 * Initialise the memory for all the arguments that needs to 116 * be passed to BL31 117 */ 118 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 119 120 /* Assign memory for TF related information */ 121 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 122 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 123 124 /* Fill BL31 related information */ 125 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 126 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 127 VERSION_1, 0); 128 129 /* Fill BL32 related information if it exists */ 130 #ifdef BL32_BASE 131 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 132 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 133 VERSION_1, 0); 134 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 135 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 136 VERSION_1, 0); 137 #endif /* BL32_BASE */ 138 139 /* Fill BL33 related information */ 140 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 141 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 142 PARAM_EP, VERSION_1, 0); 143 144 /* BL33 expects to receive the primary CPU MPID (through x0) */ 145 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 146 147 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 148 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 149 VERSION_1, 0); 150 151 return bl2_to_bl31_params; 152 } 153 154 /* Flush the TF params and the TF plat params */ 155 void bl2_plat_flush_bl31_params(void) 156 { 157 flush_dcache_range((unsigned long)&bl31_params_mem, 158 sizeof(bl2_to_bl31_params_mem_t)); 159 } 160 161 /******************************************************************************* 162 * This function returns a pointer to the shared memory that the platform 163 * has kept to point to entry point information of BL31 to BL2 164 ******************************************************************************/ 165 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 166 { 167 #if DEBUG 168 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL; 169 #endif 170 171 return &bl31_params_mem.bl31_ep_info; 172 } 173 #endif /* LOAD_IMAGE_V2 */ 174 175 /******************************************************************************* 176 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 177 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 178 * Copy it to a safe location before its reclaimed by later BL2 functionality. 179 ******************************************************************************/ 180 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, 181 struct meminfo *mem_layout) 182 { 183 /* Initialize the console to provide early debug support */ 184 arm_console_boot_init(); 185 186 /* Setup the BL2 memory layout */ 187 bl2_tzram_layout = *mem_layout; 188 189 /* Initialise the IO layer and register platform IO devices */ 190 plat_arm_io_setup(); 191 192 #if LOAD_IMAGE_V2 193 if (tb_fw_config != 0U) 194 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 195 #endif 196 } 197 198 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 199 { 200 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 201 202 generic_delay_timer_init(); 203 } 204 205 /* 206 * Perform BL2 preload setup. Currently we initialise the dynamic 207 * configuration here. 208 */ 209 void bl2_plat_preload_setup(void) 210 { 211 #if LOAD_IMAGE_V2 212 arm_bl2_dyn_cfg_init(); 213 #endif 214 } 215 216 /* 217 * Perform ARM standard platform setup. 218 */ 219 void arm_bl2_platform_setup(void) 220 { 221 /* Initialize the secure environment */ 222 plat_arm_security_setup(); 223 224 #if defined(PLAT_ARM_MEM_PROT_ADDR) 225 arm_nor_psci_do_static_mem_protect(); 226 #endif 227 } 228 229 void bl2_platform_setup(void) 230 { 231 arm_bl2_platform_setup(); 232 } 233 234 /******************************************************************************* 235 * Perform the very early platform specific architectural setup here. At the 236 * moment this is only initializes the mmu in a quick and dirty way. 237 ******************************************************************************/ 238 void arm_bl2_plat_arch_setup(void) 239 { 240 241 #if USE_COHERENT_MEM 242 /* Ensure ARM platforms dont use coherent memory in BL2 */ 243 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 244 #endif 245 246 const mmap_region_t bl_regions[] = { 247 MAP_BL2_TOTAL, 248 ARM_MAP_BL_RO, 249 #if USE_ROMLIB 250 ARM_MAP_ROMLIB_CODE, 251 ARM_MAP_ROMLIB_DATA, 252 #endif 253 {0} 254 }; 255 256 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 257 258 #ifdef AARCH32 259 enable_mmu_svc_mon(0); 260 #else 261 enable_mmu_el1(0); 262 #endif 263 264 arm_setup_romlib(); 265 } 266 267 void bl2_plat_arch_setup(void) 268 { 269 arm_bl2_plat_arch_setup(); 270 } 271 272 #if LOAD_IMAGE_V2 273 int arm_bl2_handle_post_image_load(unsigned int image_id) 274 { 275 int err = 0; 276 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 277 #ifdef SPD_opteed 278 bl_mem_params_node_t *pager_mem_params = NULL; 279 bl_mem_params_node_t *paged_mem_params = NULL; 280 #endif 281 assert(bl_mem_params); 282 283 switch (image_id) { 284 #ifdef AARCH64 285 case BL32_IMAGE_ID: 286 #ifdef SPD_opteed 287 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 288 assert(pager_mem_params); 289 290 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 291 assert(paged_mem_params); 292 293 err = parse_optee_header(&bl_mem_params->ep_info, 294 &pager_mem_params->image_info, 295 &paged_mem_params->image_info); 296 if (err != 0) { 297 WARN("OPTEE header parse error.\n"); 298 } 299 #endif 300 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 301 break; 302 #endif 303 304 case BL33_IMAGE_ID: 305 /* BL33 expects to receive the primary CPU MPID (through r0) */ 306 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 307 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 308 break; 309 310 #ifdef SCP_BL2_BASE 311 case SCP_BL2_IMAGE_ID: 312 /* The subsequent handling of SCP_BL2 is platform specific */ 313 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 314 if (err) { 315 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 316 } 317 break; 318 #endif 319 default: 320 /* Do nothing in default case */ 321 break; 322 } 323 324 return err; 325 } 326 327 /******************************************************************************* 328 * This function can be used by the platforms to update/use image 329 * information for given `image_id`. 330 ******************************************************************************/ 331 int bl2_plat_handle_post_image_load(unsigned int image_id) 332 { 333 return arm_bl2_handle_post_image_load(image_id); 334 } 335 336 #else /* LOAD_IMAGE_V2 */ 337 338 /******************************************************************************* 339 * Populate the extents of memory available for loading SCP_BL2 (if used), 340 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 341 ******************************************************************************/ 342 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 343 { 344 *scp_bl2_meminfo = bl2_tzram_layout; 345 } 346 347 /******************************************************************************* 348 * Before calling this function BL31 is loaded in memory and its entrypoint 349 * is set by load_image. This is a placeholder for the platform to change 350 * the entrypoint of BL31 and set SPSR and security state. 351 * On ARM standard platforms we only set the security state of the entrypoint 352 ******************************************************************************/ 353 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 354 entry_point_info_t *bl31_ep_info) 355 { 356 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 357 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 358 DISABLE_ALL_EXCEPTIONS); 359 } 360 361 362 /******************************************************************************* 363 * Before calling this function BL32 is loaded in memory and its entrypoint 364 * is set by load_image. This is a placeholder for the platform to change 365 * the entrypoint of BL32 and set SPSR and security state. 366 * On ARM standard platforms we only set the security state of the entrypoint 367 ******************************************************************************/ 368 #ifdef BL32_BASE 369 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 370 entry_point_info_t *bl32_ep_info) 371 { 372 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 373 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 374 } 375 376 /******************************************************************************* 377 * Populate the extents of memory available for loading BL32 378 ******************************************************************************/ 379 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 380 { 381 /* 382 * Populate the extents of memory available for loading BL32. 383 */ 384 bl32_meminfo->total_base = BL32_BASE; 385 bl32_meminfo->free_base = BL32_BASE; 386 bl32_meminfo->total_size = 387 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 388 bl32_meminfo->free_size = 389 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 390 } 391 #endif /* BL32_BASE */ 392 393 /******************************************************************************* 394 * Before calling this function BL33 is loaded in memory and its entrypoint 395 * is set by load_image. This is a placeholder for the platform to change 396 * the entrypoint of BL33 and set SPSR and security state. 397 * On ARM standard platforms we only set the security state of the entrypoint 398 ******************************************************************************/ 399 void bl2_plat_set_bl33_ep_info(image_info_t *image, 400 entry_point_info_t *bl33_ep_info) 401 { 402 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 403 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 404 } 405 406 /******************************************************************************* 407 * Populate the extents of memory available for loading BL33 408 ******************************************************************************/ 409 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 410 { 411 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 412 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 413 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 414 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 415 } 416 417 #endif /* LOAD_IMAGE_V2 */ 418