1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #if ENABLE_RME 22 #include <lib/gpt_rme/gpt_rme.h> 23 #endif /* ENABLE_RME */ 24 #ifdef SPD_opteed 25 #include <lib/optee_utils.h> 26 #endif 27 #include <lib/utils.h> 28 #if ENABLE_RME 29 #include <plat/arm/common/arm_pas_def.h> 30 #endif /* ENABLE_RME */ 31 #include <plat/arm/common/plat_arm.h> 32 #include <plat/common/platform.h> 33 34 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 35 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 36 37 /* Base address of fw_config received from BL1 */ 38 static uintptr_t config_base; 39 40 /* 41 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 42 * for `meminfo_t` data structure and fw_configs passed from BL1. 43 */ 44 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 45 46 /* Weak definitions may be overridden in specific ARM standard platform */ 47 #pragma weak bl2_early_platform_setup2 48 #pragma weak bl2_platform_setup 49 #pragma weak bl2_plat_arch_setup 50 #pragma weak bl2_plat_sec_mem_layout 51 52 #if ENABLE_RME 53 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 54 bl2_tzram_layout.total_base, \ 55 bl2_tzram_layout.total_size, \ 56 MT_MEMORY | MT_RW | MT_ROOT) 57 #else 58 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 59 bl2_tzram_layout.total_base, \ 60 bl2_tzram_layout.total_size, \ 61 MT_MEMORY | MT_RW | MT_SECURE) 62 #endif /* ENABLE_RME */ 63 64 #pragma weak arm_bl2_plat_handle_post_image_load 65 66 /******************************************************************************* 67 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 68 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 69 * Copy it to a safe location before its reclaimed by later BL2 functionality. 70 ******************************************************************************/ 71 void arm_bl2_early_platform_setup(uintptr_t fw_config, 72 struct meminfo *mem_layout) 73 { 74 /* Initialize the console to provide early debug support */ 75 arm_console_boot_init(); 76 77 /* Setup the BL2 memory layout */ 78 bl2_tzram_layout = *mem_layout; 79 80 config_base = fw_config; 81 82 /* Initialise the IO layer and register platform IO devices */ 83 plat_arm_io_setup(); 84 85 /* Load partition table */ 86 #if ARM_GPT_SUPPORT 87 partition_init(GPT_IMAGE_ID); 88 #endif /* ARM_GPT_SUPPORT */ 89 90 } 91 92 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 93 { 94 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 95 96 generic_delay_timer_init(); 97 } 98 99 /* 100 * Perform BL2 preload setup. Currently we initialise the dynamic 101 * configuration here. 102 */ 103 void bl2_plat_preload_setup(void) 104 { 105 arm_bl2_dyn_cfg_init(); 106 107 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 108 /* Always use the FIP from bank 0 */ 109 arm_set_fip_addr(0U); 110 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 111 } 112 113 /* 114 * Perform ARM standard platform setup. 115 */ 116 void arm_bl2_platform_setup(void) 117 { 118 #if !ENABLE_RME 119 /* Initialize the secure environment */ 120 plat_arm_security_setup(); 121 #endif 122 123 #if defined(PLAT_ARM_MEM_PROT_ADDR) 124 arm_nor_psci_do_static_mem_protect(); 125 #endif 126 } 127 128 void bl2_platform_setup(void) 129 { 130 arm_bl2_platform_setup(); 131 } 132 133 #if ENABLE_RME 134 135 static void arm_bl2_plat_gpt_setup(void) 136 { 137 /* 138 * The GPT library might modify the gpt regions structure to optimize 139 * the layout, so the array cannot be constant. 140 */ 141 pas_region_t pas_regions[] = { 142 ARM_PAS_KERNEL, 143 ARM_PAS_SECURE, 144 ARM_PAS_REALM, 145 ARM_PAS_EL3_DRAM, 146 ARM_PAS_GPTS, 147 ARM_PAS_KERNEL_1 148 }; 149 150 /* Initialize entire protected space to GPT_GPI_ANY. */ 151 if (gpt_init_l0_tables(GPCCR_PPS_64GB, ARM_L0_GPT_ADDR_BASE, 152 ARM_L0_GPT_SIZE) < 0) { 153 ERROR("gpt_init_l0_tables() failed!\n"); 154 panic(); 155 } 156 157 /* Carve out defined PAS ranges. */ 158 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 159 ARM_L1_GPT_ADDR_BASE, 160 ARM_L1_GPT_SIZE, 161 pas_regions, 162 (unsigned int)(sizeof(pas_regions) / 163 sizeof(pas_region_t))) < 0) { 164 ERROR("gpt_init_pas_l1_tables() failed!\n"); 165 panic(); 166 } 167 168 INFO("Enabling Granule Protection Checks\n"); 169 if (gpt_enable() < 0) { 170 ERROR("gpt_enable() failed!\n"); 171 panic(); 172 } 173 } 174 175 #endif /* ENABLE_RME */ 176 177 /******************************************************************************* 178 * Perform the very early platform specific architectural setup here. 179 * When RME is enabled the secure environment is initialised before 180 * initialising and enabling Granule Protection. 181 * This function initialises the MMU in a quick and dirty way. 182 ******************************************************************************/ 183 void arm_bl2_plat_arch_setup(void) 184 { 185 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 186 /* 187 * Ensure ARM platforms don't use coherent memory in BL2 unless 188 * cryptocell integration is enabled. 189 */ 190 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 191 #endif 192 193 const mmap_region_t bl_regions[] = { 194 MAP_BL2_TOTAL, 195 ARM_MAP_BL_RO, 196 #if USE_ROMLIB 197 ARM_MAP_ROMLIB_CODE, 198 ARM_MAP_ROMLIB_DATA, 199 #endif 200 #if ARM_CRYPTOCELL_INTEG 201 ARM_MAP_BL_COHERENT_RAM, 202 #endif 203 ARM_MAP_BL_CONFIG_REGION, 204 #if ENABLE_RME 205 ARM_MAP_L0_GPT_REGION, 206 #endif 207 {0} 208 }; 209 210 #if ENABLE_RME 211 /* Initialise the secure environment */ 212 plat_arm_security_setup(); 213 #endif 214 setup_page_tables(bl_regions, plat_arm_get_mmap()); 215 216 #ifdef __aarch64__ 217 #if ENABLE_RME 218 /* BL2 runs in EL3 when RME enabled. */ 219 assert(get_armv9_2_feat_rme_support() != 0U); 220 enable_mmu_el3(0); 221 222 /* Initialise and enable granule protection after MMU. */ 223 arm_bl2_plat_gpt_setup(); 224 #else 225 enable_mmu_el1(0); 226 #endif 227 #else 228 enable_mmu_svc_mon(0); 229 #endif 230 231 arm_setup_romlib(); 232 } 233 234 void bl2_plat_arch_setup(void) 235 { 236 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 237 238 arm_bl2_plat_arch_setup(); 239 240 /* Fill the properties struct with the info from the config dtb */ 241 fconf_populate("FW_CONFIG", config_base); 242 243 /* TB_FW_CONFIG was also loaded by BL1 */ 244 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 245 assert(tb_fw_config_info != NULL); 246 247 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 248 } 249 250 int arm_bl2_handle_post_image_load(unsigned int image_id) 251 { 252 int err = 0; 253 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 254 #ifdef SPD_opteed 255 bl_mem_params_node_t *pager_mem_params = NULL; 256 bl_mem_params_node_t *paged_mem_params = NULL; 257 #endif 258 assert(bl_mem_params != NULL); 259 260 switch (image_id) { 261 #ifdef __aarch64__ 262 case BL32_IMAGE_ID: 263 #ifdef SPD_opteed 264 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 265 assert(pager_mem_params); 266 267 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 268 assert(paged_mem_params); 269 270 err = parse_optee_header(&bl_mem_params->ep_info, 271 &pager_mem_params->image_info, 272 &paged_mem_params->image_info); 273 if (err != 0) { 274 WARN("OPTEE header parse error.\n"); 275 } 276 #endif 277 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 278 break; 279 #endif 280 281 case BL33_IMAGE_ID: 282 /* BL33 expects to receive the primary CPU MPID (through r0) */ 283 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 284 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 285 break; 286 287 #ifdef SCP_BL2_BASE 288 case SCP_BL2_IMAGE_ID: 289 /* The subsequent handling of SCP_BL2 is platform specific */ 290 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 291 if (err) { 292 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 293 } 294 break; 295 #endif 296 default: 297 /* Do nothing in default case */ 298 break; 299 } 300 301 return err; 302 } 303 304 /******************************************************************************* 305 * This function can be used by the platforms to update/use image 306 * information for given `image_id`. 307 ******************************************************************************/ 308 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 309 { 310 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 311 /* For Secure Partitions we don't need post processing */ 312 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 313 (image_id < MAX_NUMBER_IDS)) { 314 return 0; 315 } 316 #endif 317 return arm_bl2_handle_post_image_load(image_id); 318 } 319 320 int bl2_plat_handle_post_image_load(unsigned int image_id) 321 { 322 return arm_bl2_plat_handle_post_image_load(image_id); 323 } 324