1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/generic_delay_timer.h> 10 #include <plat/common/platform.h> 11 #include <platform_def.h> 12 13 #include <plat_arm.h> 14 15 #pragma weak bl2_el3_early_platform_setup 16 #pragma weak bl2_el3_plat_arch_setup 17 #pragma weak bl2_el3_plat_prepare_exit 18 19 #define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \ 20 bl2_el3_tzram_layout.total_base, \ 21 bl2_el3_tzram_layout.total_size, \ 22 MT_MEMORY | MT_RW | MT_SECURE) 23 24 static meminfo_t bl2_el3_tzram_layout; 25 26 /* 27 * Perform arm specific early platform setup. At this moment we only initialize 28 * the console and the memory layout. 29 */ 30 void arm_bl2_el3_early_platform_setup(void) 31 { 32 /* Initialize the console to provide early debug support */ 33 arm_console_boot_init(); 34 35 /* 36 * Allow BL2 to see the whole Trusted RAM. This is determined 37 * statically since we cannot rely on BL1 passing this information 38 * in the BL2_AT_EL3 case. 39 */ 40 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE; 41 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE; 42 43 /* Initialise the IO layer and register platform IO devices */ 44 plat_arm_io_setup(); 45 } 46 47 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 48 u_register_t arg1 __unused, 49 u_register_t arg2 __unused, 50 u_register_t arg3 __unused) 51 { 52 arm_bl2_el3_early_platform_setup(); 53 54 /* 55 * Initialize Interconnect for this cluster during cold boot. 56 * No need for locks as no other CPU is active. 57 */ 58 plat_arm_interconnect_init(); 59 /* 60 * Enable Interconnect coherency for the primary CPU's cluster. 61 */ 62 plat_arm_interconnect_enter_coherency(); 63 64 generic_delay_timer_init(); 65 } 66 67 /******************************************************************************* 68 * Perform the very early platform specific architectural setup here. At the 69 * moment this is only initializes the mmu in a quick and dirty way. 70 ******************************************************************************/ 71 void arm_bl2_el3_plat_arch_setup(void) 72 { 73 74 #if USE_COHERENT_MEM 75 /* Ensure ARM platforms dont use coherent memory in BL2_AT_EL3 */ 76 assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U); 77 #endif 78 79 const mmap_region_t bl_regions[] = { 80 MAP_BL2_EL3_TOTAL, 81 ARM_MAP_BL_RO, 82 {0} 83 }; 84 85 setup_page_tables(bl_regions, plat_arm_get_mmap()); 86 87 #ifdef AARCH32 88 enable_mmu_svc_mon(0); 89 #else 90 enable_mmu_el3(0); 91 #endif 92 } 93 94 void bl2_el3_plat_arch_setup(void) 95 { 96 arm_bl2_el3_plat_arch_setup(); 97 } 98 99 void bl2_el3_plat_prepare_exit(void) 100 { 101 } 102