1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arm_def.h> 33 #include <bl_common.h> 34 #include <cci.h> 35 #include <console.h> 36 #include <platform_def.h> 37 #include <plat_arm.h> 38 #include "../../bl1/bl1_private.h" 39 40 41 #if USE_COHERENT_MEM 42 /* 43 * The next 2 constants identify the extents of the coherent memory region. 44 * These addresses are used by the MMU setup code and therefore they must be 45 * page-aligned. It is the responsibility of the linker script to ensure that 46 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 47 * page-aligned addresses. 48 */ 49 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 50 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 51 #endif 52 53 54 /* Weak definitions may be overridden in specific ARM standard platform */ 55 #pragma weak bl1_early_platform_setup 56 #pragma weak bl1_plat_arch_setup 57 #pragma weak bl1_platform_setup 58 #pragma weak bl1_plat_sec_mem_layout 59 #pragma weak bl1_plat_set_bl2_ep_info 60 61 62 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 63 static meminfo_t bl1_tzram_layout; 64 65 meminfo_t *bl1_plat_sec_mem_layout(void) 66 { 67 return &bl1_tzram_layout; 68 } 69 70 /******************************************************************************* 71 * BL1 specific platform actions shared between ARM standard platforms. 72 ******************************************************************************/ 73 void arm_bl1_early_platform_setup(void) 74 { 75 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 76 77 /* Initialize the console to provide early debug support */ 78 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 79 ARM_CONSOLE_BAUDRATE); 80 81 /* Allow BL1 to see the whole Trusted RAM */ 82 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 83 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 84 85 /* Calculate how much RAM BL1 is using and how much remains free */ 86 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 87 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 88 reserve_mem(&bl1_tzram_layout.free_base, 89 &bl1_tzram_layout.free_size, 90 BL1_RAM_BASE, 91 bl1_size); 92 } 93 94 void bl1_early_platform_setup(void) 95 { 96 arm_bl1_early_platform_setup(); 97 98 /* 99 * Initialize CCI for this cluster during cold boot. 100 * No need for locks as no other CPU is active. 101 */ 102 arm_cci_init(); 103 /* 104 * Enable CCI coherency for the primary CPU's cluster. 105 */ 106 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 107 } 108 109 /****************************************************************************** 110 * Perform the very early platform specific architecture setup shared between 111 * ARM standard platforms. This only does basic initialization. Later 112 * architectural setup (bl1_arch_setup()) does not do anything platform 113 * specific. 114 *****************************************************************************/ 115 void arm_bl1_plat_arch_setup(void) 116 { 117 arm_configure_mmu_el3(bl1_tzram_layout.total_base, 118 bl1_tzram_layout.total_size, 119 BL1_RO_BASE, 120 BL1_RO_LIMIT 121 #if USE_COHERENT_MEM 122 , BL1_COHERENT_RAM_BASE, 123 BL1_COHERENT_RAM_LIMIT 124 #endif 125 ); 126 } 127 128 void bl1_plat_arch_setup(void) 129 { 130 arm_bl1_plat_arch_setup(); 131 } 132 133 /* 134 * Perform the platform specific architecture setup shared between 135 * ARM standard platforms. 136 */ 137 void arm_bl1_platform_setup(void) 138 { 139 /* Initialise the IO layer and register platform IO devices */ 140 plat_arm_io_setup(); 141 } 142 143 void bl1_platform_setup(void) 144 { 145 arm_bl1_platform_setup(); 146 } 147 148 /******************************************************************************* 149 * Before calling this function BL2 is loaded in memory and its entrypoint 150 * is set by load_image. This is a placeholder for the platform to change 151 * the entrypoint of BL2 and set SPSR and security state. 152 * On ARM standard platforms we only set the security state of the entrypoint 153 ******************************************************************************/ 154 void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, 155 entry_point_info_t *bl2_ep) 156 { 157 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); 158 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 159 } 160