1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arm_def.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <platform_def.h> 36 #include <plat_arm.h> 37 #include <sp805.h> 38 #include <utils.h> 39 #include <xlat_tables.h> 40 #include "../../../bl1/bl1_private.h" 41 42 43 #if USE_COHERENT_MEM 44 /* 45 * The next 2 constants identify the extents of the coherent memory region. 46 * These addresses are used by the MMU setup code and therefore they must be 47 * page-aligned. It is the responsibility of the linker script to ensure that 48 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 49 * page-aligned addresses. 50 */ 51 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 52 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 53 #endif 54 55 56 /* Weak definitions may be overridden in specific ARM standard platform */ 57 #pragma weak bl1_early_platform_setup 58 #pragma weak bl1_plat_arch_setup 59 #pragma weak bl1_platform_setup 60 #pragma weak bl1_plat_sec_mem_layout 61 62 63 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 64 static meminfo_t bl1_tzram_layout; 65 66 meminfo_t *bl1_plat_sec_mem_layout(void) 67 { 68 return &bl1_tzram_layout; 69 } 70 71 /******************************************************************************* 72 * BL1 specific platform actions shared between ARM standard platforms. 73 ******************************************************************************/ 74 void arm_bl1_early_platform_setup(void) 75 { 76 77 #if !ARM_DISABLE_TRUSTED_WDOG 78 /* Enable watchdog */ 79 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 80 #endif 81 82 /* Initialize the console to provide early debug support */ 83 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 84 ARM_CONSOLE_BAUDRATE); 85 86 /* Allow BL1 to see the whole Trusted RAM */ 87 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 88 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 89 90 #if !LOAD_IMAGE_V2 91 /* Calculate how much RAM BL1 is using and how much remains free */ 92 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 93 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 94 reserve_mem(&bl1_tzram_layout.free_base, 95 &bl1_tzram_layout.free_size, 96 BL1_RAM_BASE, 97 BL1_RAM_LIMIT - BL1_RAM_BASE); 98 #endif /* LOAD_IMAGE_V2 */ 99 } 100 101 void bl1_early_platform_setup(void) 102 { 103 arm_bl1_early_platform_setup(); 104 105 /* 106 * Initialize Interconnect for this cluster during cold boot. 107 * No need for locks as no other CPU is active. 108 */ 109 plat_arm_interconnect_init(); 110 /* 111 * Enable Interconnect coherency for the primary CPU's cluster. 112 */ 113 plat_arm_interconnect_enter_coherency(); 114 } 115 116 /****************************************************************************** 117 * Perform the very early platform specific architecture setup shared between 118 * ARM standard platforms. This only does basic initialization. Later 119 * architectural setup (bl1_arch_setup()) does not do anything platform 120 * specific. 121 *****************************************************************************/ 122 void arm_bl1_plat_arch_setup(void) 123 { 124 arm_setup_page_tables(bl1_tzram_layout.total_base, 125 bl1_tzram_layout.total_size, 126 BL_CODE_BASE, 127 BL1_CODE_LIMIT, 128 BL1_RO_DATA_BASE, 129 BL1_RO_DATA_LIMIT 130 #if USE_COHERENT_MEM 131 , BL1_COHERENT_RAM_BASE, 132 BL1_COHERENT_RAM_LIMIT 133 #endif 134 ); 135 #ifdef AARCH32 136 enable_mmu_secure(0); 137 #else 138 enable_mmu_el3(0); 139 #endif /* AARCH32 */ 140 } 141 142 void bl1_plat_arch_setup(void) 143 { 144 arm_bl1_plat_arch_setup(); 145 } 146 147 /* 148 * Perform the platform specific architecture setup shared between 149 * ARM standard platforms. 150 */ 151 void arm_bl1_platform_setup(void) 152 { 153 /* Initialise the IO layer and register platform IO devices */ 154 plat_arm_io_setup(); 155 } 156 157 void bl1_platform_setup(void) 158 { 159 arm_bl1_platform_setup(); 160 } 161 162 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 163 { 164 #if !ARM_DISABLE_TRUSTED_WDOG 165 /* Disable watchdog before leaving BL1 */ 166 sp805_stop(ARM_SP805_TWDG_BASE); 167 #endif 168 169 #ifdef EL3_PAYLOAD_BASE 170 /* 171 * Program the EL3 payload's entry point address into the CPUs mailbox 172 * in order to release secondary CPUs from their holding pen and make 173 * them jump there. 174 */ 175 arm_program_trusted_mailbox(ep_info->pc); 176 dsbsy(); 177 sev(); 178 #endif 179 } 180