1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <drivers/arm/sp805.h> 15 #include <lib/utils.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/common/platform.h> 18 19 #include <plat_arm.h> 20 21 /* Weak definitions may be overridden in specific ARM standard platform */ 22 #pragma weak bl1_early_platform_setup 23 #pragma weak bl1_plat_arch_setup 24 #pragma weak bl1_platform_setup 25 #pragma weak bl1_plat_sec_mem_layout 26 #pragma weak bl1_plat_prepare_exit 27 #pragma weak bl1_plat_get_next_image_id 28 #pragma weak plat_arm_bl1_fwu_needed 29 30 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 31 bl1_tzram_layout.total_base, \ 32 bl1_tzram_layout.total_size, \ 33 MT_MEMORY | MT_RW | MT_SECURE) 34 /* 35 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 36 * otherwise one region is defined containing both 37 */ 38 #if SEPARATE_CODE_AND_RODATA 39 #define MAP_BL1_RO MAP_REGION_FLAT( \ 40 BL_CODE_BASE, \ 41 BL1_CODE_END - BL_CODE_BASE, \ 42 MT_CODE | MT_SECURE), \ 43 MAP_REGION_FLAT( \ 44 BL1_RO_DATA_BASE, \ 45 BL1_RO_DATA_END \ 46 - BL_RO_DATA_BASE, \ 47 MT_RO_DATA | MT_SECURE) 48 #else 49 #define MAP_BL1_RO MAP_REGION_FLAT( \ 50 BL_CODE_BASE, \ 51 BL1_CODE_END - BL_CODE_BASE, \ 52 MT_CODE | MT_SECURE) 53 #endif 54 55 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 56 static meminfo_t bl1_tzram_layout; 57 58 struct meminfo *bl1_plat_sec_mem_layout(void) 59 { 60 return &bl1_tzram_layout; 61 } 62 63 /******************************************************************************* 64 * BL1 specific platform actions shared between ARM standard platforms. 65 ******************************************************************************/ 66 void arm_bl1_early_platform_setup(void) 67 { 68 69 #if !ARM_DISABLE_TRUSTED_WDOG 70 /* Enable watchdog */ 71 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 72 #endif 73 74 /* Initialize the console to provide early debug support */ 75 arm_console_boot_init(); 76 77 /* Allow BL1 to see the whole Trusted RAM */ 78 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 79 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 80 } 81 82 void bl1_early_platform_setup(void) 83 { 84 arm_bl1_early_platform_setup(); 85 86 /* 87 * Initialize Interconnect for this cluster during cold boot. 88 * No need for locks as no other CPU is active. 89 */ 90 plat_arm_interconnect_init(); 91 /* 92 * Enable Interconnect coherency for the primary CPU's cluster. 93 */ 94 plat_arm_interconnect_enter_coherency(); 95 } 96 97 /****************************************************************************** 98 * Perform the very early platform specific architecture setup shared between 99 * ARM standard platforms. This only does basic initialization. Later 100 * architectural setup (bl1_arch_setup()) does not do anything platform 101 * specific. 102 *****************************************************************************/ 103 void arm_bl1_plat_arch_setup(void) 104 { 105 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 106 /* 107 * Ensure ARM platforms don't use coherent memory in BL1 unless 108 * cryptocell integration is enabled. 109 */ 110 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 111 #endif 112 113 const mmap_region_t bl_regions[] = { 114 MAP_BL1_TOTAL, 115 MAP_BL1_RO, 116 #if USE_ROMLIB 117 ARM_MAP_ROMLIB_CODE, 118 ARM_MAP_ROMLIB_DATA, 119 #endif 120 #if ARM_CRYPTOCELL_INTEG 121 ARM_MAP_BL_COHERENT_RAM, 122 #endif 123 {0} 124 }; 125 126 setup_page_tables(bl_regions, plat_arm_get_mmap()); 127 #ifdef AARCH32 128 enable_mmu_svc_mon(0); 129 #else 130 enable_mmu_el3(0); 131 #endif /* AARCH32 */ 132 133 arm_setup_romlib(); 134 } 135 136 void bl1_plat_arch_setup(void) 137 { 138 arm_bl1_plat_arch_setup(); 139 } 140 141 /* 142 * Perform the platform specific architecture setup shared between 143 * ARM standard platforms. 144 */ 145 void arm_bl1_platform_setup(void) 146 { 147 /* Initialise the IO layer and register platform IO devices */ 148 plat_arm_io_setup(); 149 arm_load_tb_fw_config(); 150 #if TRUSTED_BOARD_BOOT 151 /* Share the Mbed TLS heap info with other images */ 152 arm_bl1_set_mbedtls_heap(); 153 #endif /* TRUSTED_BOARD_BOOT */ 154 155 /* 156 * Allow access to the System counter timer module and program 157 * counter frequency for non secure images during FWU 158 */ 159 arm_configure_sys_timer(); 160 write_cntfrq_el0(plat_get_syscnt_freq2()); 161 } 162 163 void bl1_platform_setup(void) 164 { 165 arm_bl1_platform_setup(); 166 } 167 168 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 169 { 170 #if !ARM_DISABLE_TRUSTED_WDOG 171 /* Disable watchdog before leaving BL1 */ 172 sp805_stop(ARM_SP805_TWDG_BASE); 173 #endif 174 175 #ifdef EL3_PAYLOAD_BASE 176 /* 177 * Program the EL3 payload's entry point address into the CPUs mailbox 178 * in order to release secondary CPUs from their holding pen and make 179 * them jump there. 180 */ 181 plat_arm_program_trusted_mailbox(ep_info->pc); 182 dsbsy(); 183 sev(); 184 #endif 185 } 186 187 /* 188 * On Arm platforms, the FWU process is triggered when the FIP image has 189 * been tampered with. 190 */ 191 int plat_arm_bl1_fwu_needed(void) 192 { 193 return (arm_io_is_toc_valid() != 1); 194 } 195 196 /******************************************************************************* 197 * The following function checks if Firmware update is needed, 198 * by checking if TOC in FIP image is valid or not. 199 ******************************************************************************/ 200 unsigned int bl1_plat_get_next_image_id(void) 201 { 202 if (plat_arm_bl1_fwu_needed() != 0) 203 return NS_BL1U_IMAGE_ID; 204 205 return BL2_IMAGE_ID; 206 } 207