1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <drivers/arm/sp805.h> 15 #include <lib/utils.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak bl1_early_platform_setup 22 #pragma weak bl1_plat_arch_setup 23 #pragma weak bl1_platform_setup 24 #pragma weak bl1_plat_sec_mem_layout 25 #pragma weak bl1_plat_prepare_exit 26 #pragma weak bl1_plat_get_next_image_id 27 #pragma weak plat_arm_bl1_fwu_needed 28 29 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 30 bl1_tzram_layout.total_base, \ 31 bl1_tzram_layout.total_size, \ 32 MT_MEMORY | MT_RW | MT_SECURE) 33 /* 34 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 35 * otherwise one region is defined containing both 36 */ 37 #if SEPARATE_CODE_AND_RODATA 38 #define MAP_BL1_RO MAP_REGION_FLAT( \ 39 BL_CODE_BASE, \ 40 BL1_CODE_END - BL_CODE_BASE, \ 41 MT_CODE | MT_SECURE), \ 42 MAP_REGION_FLAT( \ 43 BL1_RO_DATA_BASE, \ 44 BL1_RO_DATA_END \ 45 - BL_RO_DATA_BASE, \ 46 MT_RO_DATA | MT_SECURE) 47 #else 48 #define MAP_BL1_RO MAP_REGION_FLAT( \ 49 BL_CODE_BASE, \ 50 BL1_CODE_END - BL_CODE_BASE, \ 51 MT_CODE | MT_SECURE) 52 #endif 53 54 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 55 static meminfo_t bl1_tzram_layout; 56 57 struct meminfo *bl1_plat_sec_mem_layout(void) 58 { 59 return &bl1_tzram_layout; 60 } 61 62 /******************************************************************************* 63 * BL1 specific platform actions shared between ARM standard platforms. 64 ******************************************************************************/ 65 void arm_bl1_early_platform_setup(void) 66 { 67 68 #if !ARM_DISABLE_TRUSTED_WDOG 69 /* Enable watchdog */ 70 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 71 #endif 72 73 /* Initialize the console to provide early debug support */ 74 arm_console_boot_init(); 75 76 /* Allow BL1 to see the whole Trusted RAM */ 77 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 78 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 79 } 80 81 void bl1_early_platform_setup(void) 82 { 83 arm_bl1_early_platform_setup(); 84 85 /* 86 * Initialize Interconnect for this cluster during cold boot. 87 * No need for locks as no other CPU is active. 88 */ 89 plat_arm_interconnect_init(); 90 /* 91 * Enable Interconnect coherency for the primary CPU's cluster. 92 */ 93 plat_arm_interconnect_enter_coherency(); 94 } 95 96 /****************************************************************************** 97 * Perform the very early platform specific architecture setup shared between 98 * ARM standard platforms. This only does basic initialization. Later 99 * architectural setup (bl1_arch_setup()) does not do anything platform 100 * specific. 101 *****************************************************************************/ 102 void arm_bl1_plat_arch_setup(void) 103 { 104 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 105 /* 106 * Ensure ARM platforms don't use coherent memory in BL1 unless 107 * cryptocell integration is enabled. 108 */ 109 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 110 #endif 111 112 const mmap_region_t bl_regions[] = { 113 MAP_BL1_TOTAL, 114 MAP_BL1_RO, 115 #if USE_ROMLIB 116 ARM_MAP_ROMLIB_CODE, 117 ARM_MAP_ROMLIB_DATA, 118 #endif 119 #if ARM_CRYPTOCELL_INTEG 120 ARM_MAP_BL_COHERENT_RAM, 121 #endif 122 {0} 123 }; 124 125 setup_page_tables(bl_regions, plat_arm_get_mmap()); 126 #ifdef AARCH32 127 enable_mmu_svc_mon(0); 128 #else 129 enable_mmu_el3(0); 130 #endif /* AARCH32 */ 131 132 arm_setup_romlib(); 133 } 134 135 void bl1_plat_arch_setup(void) 136 { 137 arm_bl1_plat_arch_setup(); 138 } 139 140 /* 141 * Perform the platform specific architecture setup shared between 142 * ARM standard platforms. 143 */ 144 void arm_bl1_platform_setup(void) 145 { 146 /* Initialise the IO layer and register platform IO devices */ 147 plat_arm_io_setup(); 148 arm_load_tb_fw_config(); 149 #if TRUSTED_BOARD_BOOT 150 /* Share the Mbed TLS heap info with other images */ 151 arm_bl1_set_mbedtls_heap(); 152 #endif /* TRUSTED_BOARD_BOOT */ 153 154 /* 155 * Allow access to the System counter timer module and program 156 * counter frequency for non secure images during FWU 157 */ 158 arm_configure_sys_timer(); 159 write_cntfrq_el0(plat_get_syscnt_freq2()); 160 } 161 162 void bl1_platform_setup(void) 163 { 164 arm_bl1_platform_setup(); 165 } 166 167 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 168 { 169 #if !ARM_DISABLE_TRUSTED_WDOG 170 /* Disable watchdog before leaving BL1 */ 171 sp805_stop(ARM_SP805_TWDG_BASE); 172 #endif 173 174 #ifdef EL3_PAYLOAD_BASE 175 /* 176 * Program the EL3 payload's entry point address into the CPUs mailbox 177 * in order to release secondary CPUs from their holding pen and make 178 * them jump there. 179 */ 180 plat_arm_program_trusted_mailbox(ep_info->pc); 181 dsbsy(); 182 sev(); 183 #endif 184 } 185 186 /* 187 * On Arm platforms, the FWU process is triggered when the FIP image has 188 * been tampered with. 189 */ 190 int plat_arm_bl1_fwu_needed(void) 191 { 192 return (arm_io_is_toc_valid() != 1); 193 } 194 195 /******************************************************************************* 196 * The following function checks if Firmware update is needed, 197 * by checking if TOC in FIP image is valid or not. 198 ******************************************************************************/ 199 unsigned int bl1_plat_get_next_image_id(void) 200 { 201 if (plat_arm_bl1_fwu_needed() != 0) 202 return NS_BL1U_IMAGE_ID; 203 204 return BL2_IMAGE_ID; 205 } 206