1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <lib/fconf/fconf.h> 15 #include <lib/utils.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak bl1_early_platform_setup 22 #pragma weak bl1_plat_arch_setup 23 #pragma weak bl1_plat_sec_mem_layout 24 #pragma weak bl1_plat_prepare_exit 25 #pragma weak bl1_plat_get_next_image_id 26 #pragma weak plat_arm_bl1_fwu_needed 27 28 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 29 bl1_tzram_layout.total_base, \ 30 bl1_tzram_layout.total_size, \ 31 MT_MEMORY | MT_RW | MT_SECURE) 32 /* 33 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 34 * otherwise one region is defined containing both 35 */ 36 #if SEPARATE_CODE_AND_RODATA 37 #define MAP_BL1_RO MAP_REGION_FLAT( \ 38 BL_CODE_BASE, \ 39 BL1_CODE_END - BL_CODE_BASE, \ 40 MT_CODE | MT_SECURE), \ 41 MAP_REGION_FLAT( \ 42 BL1_RO_DATA_BASE, \ 43 BL1_RO_DATA_END \ 44 - BL_RO_DATA_BASE, \ 45 MT_RO_DATA | MT_SECURE) 46 #else 47 #define MAP_BL1_RO MAP_REGION_FLAT( \ 48 BL_CODE_BASE, \ 49 BL1_CODE_END - BL_CODE_BASE, \ 50 MT_CODE | MT_SECURE) 51 #endif 52 53 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 54 static meminfo_t bl1_tzram_layout; 55 56 struct meminfo *bl1_plat_sec_mem_layout(void) 57 { 58 return &bl1_tzram_layout; 59 } 60 61 /******************************************************************************* 62 * BL1 specific platform actions shared between ARM standard platforms. 63 ******************************************************************************/ 64 void arm_bl1_early_platform_setup(void) 65 { 66 67 #if !ARM_DISABLE_TRUSTED_WDOG 68 /* Enable watchdog */ 69 plat_arm_secure_wdt_start(); 70 #endif 71 72 /* Initialize the console to provide early debug support */ 73 arm_console_boot_init(); 74 75 /* Allow BL1 to see the whole Trusted RAM */ 76 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 77 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 78 } 79 80 void bl1_early_platform_setup(void) 81 { 82 arm_bl1_early_platform_setup(); 83 84 /* 85 * Initialize Interconnect for this cluster during cold boot. 86 * No need for locks as no other CPU is active. 87 */ 88 plat_arm_interconnect_init(); 89 /* 90 * Enable Interconnect coherency for the primary CPU's cluster. 91 */ 92 plat_arm_interconnect_enter_coherency(); 93 } 94 95 /****************************************************************************** 96 * Perform the very early platform specific architecture setup shared between 97 * ARM standard platforms. This only does basic initialization. Later 98 * architectural setup (bl1_arch_setup()) does not do anything platform 99 * specific. 100 *****************************************************************************/ 101 void arm_bl1_plat_arch_setup(void) 102 { 103 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 104 /* 105 * Ensure ARM platforms don't use coherent memory in BL1 unless 106 * cryptocell integration is enabled. 107 */ 108 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 109 #endif 110 111 const mmap_region_t bl_regions[] = { 112 MAP_BL1_TOTAL, 113 MAP_BL1_RO, 114 #if USE_ROMLIB 115 ARM_MAP_ROMLIB_CODE, 116 ARM_MAP_ROMLIB_DATA, 117 #endif 118 #if ARM_CRYPTOCELL_INTEG 119 ARM_MAP_BL_COHERENT_RAM, 120 #endif 121 {0} 122 }; 123 124 setup_page_tables(bl_regions, plat_arm_get_mmap()); 125 #ifdef __aarch64__ 126 enable_mmu_el3(0); 127 #else 128 enable_mmu_svc_mon(0); 129 #endif /* __aarch64__ */ 130 131 arm_setup_romlib(); 132 } 133 134 void bl1_plat_arch_setup(void) 135 { 136 arm_bl1_plat_arch_setup(); 137 } 138 139 /* 140 * Perform the platform specific architecture setup shared between 141 * ARM standard platforms. 142 */ 143 void arm_bl1_platform_setup(void) 144 { 145 /* Initialise the IO layer and register platform IO devices */ 146 plat_arm_io_setup(); 147 148 /* Load fw config */ 149 fconf_load_config(); 150 151 #if TRUSTED_BOARD_BOOT 152 /* Share the Mbed TLS heap info with other images */ 153 arm_bl1_set_mbedtls_heap(); 154 #endif /* TRUSTED_BOARD_BOOT */ 155 156 /* 157 * Allow access to the System counter timer module and program 158 * counter frequency for non secure images during FWU 159 */ 160 #ifdef ARM_SYS_TIMCTL_BASE 161 arm_configure_sys_timer(); 162 #endif 163 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) 164 write_cntfrq_el0(plat_get_syscnt_freq2()); 165 #endif 166 } 167 168 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 169 { 170 #if !ARM_DISABLE_TRUSTED_WDOG 171 /* Disable watchdog before leaving BL1 */ 172 plat_arm_secure_wdt_stop(); 173 #endif 174 175 #ifdef EL3_PAYLOAD_BASE 176 /* 177 * Program the EL3 payload's entry point address into the CPUs mailbox 178 * in order to release secondary CPUs from their holding pen and make 179 * them jump there. 180 */ 181 plat_arm_program_trusted_mailbox(ep_info->pc); 182 dsbsy(); 183 sev(); 184 #endif 185 } 186 187 /* 188 * On Arm platforms, the FWU process is triggered when the FIP image has 189 * been tampered with. 190 */ 191 bool plat_arm_bl1_fwu_needed(void) 192 { 193 return !arm_io_is_toc_valid(); 194 } 195 196 /******************************************************************************* 197 * The following function checks if Firmware update is needed, 198 * by checking if TOC in FIP image is valid or not. 199 ******************************************************************************/ 200 unsigned int bl1_plat_get_next_image_id(void) 201 { 202 return plat_arm_bl1_fwu_needed() ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID; 203 } 204