1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arm_def.h> 33 #include <bl_common.h> 34 #include <cci.h> 35 #include <console.h> 36 #include <platform_def.h> 37 #include <plat_arm.h> 38 #include <sp805.h> 39 #include "../../../bl1/bl1_private.h" 40 41 42 #if USE_COHERENT_MEM 43 /* 44 * The next 2 constants identify the extents of the coherent memory region. 45 * These addresses are used by the MMU setup code and therefore they must be 46 * page-aligned. It is the responsibility of the linker script to ensure that 47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 48 * page-aligned addresses. 49 */ 50 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 51 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 52 #endif 53 54 55 /* Weak definitions may be overridden in specific ARM standard platform */ 56 #pragma weak bl1_early_platform_setup 57 #pragma weak bl1_plat_arch_setup 58 #pragma weak bl1_platform_setup 59 #pragma weak bl1_plat_sec_mem_layout 60 #pragma weak bl1_plat_set_bl2_ep_info 61 62 63 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 64 static meminfo_t bl1_tzram_layout; 65 66 meminfo_t *bl1_plat_sec_mem_layout(void) 67 { 68 return &bl1_tzram_layout; 69 } 70 71 /******************************************************************************* 72 * BL1 specific platform actions shared between ARM standard platforms. 73 ******************************************************************************/ 74 void arm_bl1_early_platform_setup(void) 75 { 76 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 77 78 #if !ARM_DISABLE_TRUSTED_WDOG 79 /* Enable watchdog */ 80 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 81 #endif 82 83 /* Initialize the console to provide early debug support */ 84 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 85 ARM_CONSOLE_BAUDRATE); 86 87 /* Allow BL1 to see the whole Trusted RAM */ 88 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 89 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 90 91 /* Calculate how much RAM BL1 is using and how much remains free */ 92 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 93 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 94 reserve_mem(&bl1_tzram_layout.free_base, 95 &bl1_tzram_layout.free_size, 96 BL1_RAM_BASE, 97 bl1_size); 98 } 99 100 void bl1_early_platform_setup(void) 101 { 102 arm_bl1_early_platform_setup(); 103 104 /* 105 * Initialize CCI for this cluster during cold boot. 106 * No need for locks as no other CPU is active. 107 */ 108 arm_cci_init(); 109 /* 110 * Enable CCI coherency for the primary CPU's cluster. 111 */ 112 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 113 } 114 115 /****************************************************************************** 116 * Perform the very early platform specific architecture setup shared between 117 * ARM standard platforms. This only does basic initialization. Later 118 * architectural setup (bl1_arch_setup()) does not do anything platform 119 * specific. 120 *****************************************************************************/ 121 void arm_bl1_plat_arch_setup(void) 122 { 123 arm_configure_mmu_el3(bl1_tzram_layout.total_base, 124 bl1_tzram_layout.total_size, 125 BL1_RO_BASE, 126 BL1_RO_LIMIT 127 #if USE_COHERENT_MEM 128 , BL1_COHERENT_RAM_BASE, 129 BL1_COHERENT_RAM_LIMIT 130 #endif 131 ); 132 } 133 134 void bl1_plat_arch_setup(void) 135 { 136 arm_bl1_plat_arch_setup(); 137 } 138 139 /* 140 * Perform the platform specific architecture setup shared between 141 * ARM standard platforms. 142 */ 143 void arm_bl1_platform_setup(void) 144 { 145 /* Initialise the IO layer and register platform IO devices */ 146 plat_arm_io_setup(); 147 } 148 149 void bl1_platform_setup(void) 150 { 151 arm_bl1_platform_setup(); 152 } 153 154 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 155 { 156 #if !ARM_DISABLE_TRUSTED_WDOG 157 /* Disable watchdog before leaving BL1 */ 158 sp805_stop(ARM_SP805_TWDG_BASE); 159 #endif 160 161 #ifdef EL3_PAYLOAD_BASE 162 /* 163 * Program the EL3 payload's entry point address into the CPUs mailbox 164 * in order to release secondary CPUs from their holding pen and make 165 * them jump there. 166 */ 167 arm_program_trusted_mailbox(ep_info->pc); 168 dsbsy(); 169 sev(); 170 #endif 171 } 172 173 /******************************************************************************* 174 * Before calling this function BL2 is loaded in memory and its entrypoint 175 * is set by load_image. This is a placeholder for the platform to change 176 * the entrypoint of BL2 and set SPSR and security state. 177 * On ARM standard platforms we only set the security state of the entrypoint 178 ******************************************************************************/ 179 void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, 180 entry_point_info_t *bl2_ep) 181 { 182 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); 183 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 184 } 185