1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <drivers/arm/sp805.h> 15 #include <lib/utils.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/common/platform.h> 18 19 #include <plat_arm.h> 20 21 #include "../../../bl1/bl1_private.h" 22 23 /* Weak definitions may be overridden in specific ARM standard platform */ 24 #pragma weak bl1_early_platform_setup 25 #pragma weak bl1_plat_arch_setup 26 #pragma weak bl1_platform_setup 27 #pragma weak bl1_plat_sec_mem_layout 28 #pragma weak bl1_plat_prepare_exit 29 #pragma weak bl1_plat_get_next_image_id 30 #pragma weak plat_arm_bl1_fwu_needed 31 32 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 33 bl1_tzram_layout.total_base, \ 34 bl1_tzram_layout.total_size, \ 35 MT_MEMORY | MT_RW | MT_SECURE) 36 /* 37 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 38 * otherwise one region is defined containing both 39 */ 40 #if SEPARATE_CODE_AND_RODATA 41 #define MAP_BL1_RO MAP_REGION_FLAT( \ 42 BL_CODE_BASE, \ 43 BL1_CODE_END - BL_CODE_BASE, \ 44 MT_CODE | MT_SECURE), \ 45 MAP_REGION_FLAT( \ 46 BL1_RO_DATA_BASE, \ 47 BL1_RO_DATA_END \ 48 - BL_RO_DATA_BASE, \ 49 MT_RO_DATA | MT_SECURE) 50 #else 51 #define MAP_BL1_RO MAP_REGION_FLAT( \ 52 BL_CODE_BASE, \ 53 BL1_CODE_END - BL_CODE_BASE, \ 54 MT_CODE | MT_SECURE) 55 #endif 56 57 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 58 static meminfo_t bl1_tzram_layout; 59 60 struct meminfo *bl1_plat_sec_mem_layout(void) 61 { 62 return &bl1_tzram_layout; 63 } 64 65 /******************************************************************************* 66 * BL1 specific platform actions shared between ARM standard platforms. 67 ******************************************************************************/ 68 void arm_bl1_early_platform_setup(void) 69 { 70 71 #if !ARM_DISABLE_TRUSTED_WDOG 72 /* Enable watchdog */ 73 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 74 #endif 75 76 /* Initialize the console to provide early debug support */ 77 arm_console_boot_init(); 78 79 /* Allow BL1 to see the whole Trusted RAM */ 80 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 81 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 82 } 83 84 void bl1_early_platform_setup(void) 85 { 86 arm_bl1_early_platform_setup(); 87 88 /* 89 * Initialize Interconnect for this cluster during cold boot. 90 * No need for locks as no other CPU is active. 91 */ 92 plat_arm_interconnect_init(); 93 /* 94 * Enable Interconnect coherency for the primary CPU's cluster. 95 */ 96 plat_arm_interconnect_enter_coherency(); 97 } 98 99 /****************************************************************************** 100 * Perform the very early platform specific architecture setup shared between 101 * ARM standard platforms. This only does basic initialization. Later 102 * architectural setup (bl1_arch_setup()) does not do anything platform 103 * specific. 104 *****************************************************************************/ 105 void arm_bl1_plat_arch_setup(void) 106 { 107 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 108 /* 109 * Ensure ARM platforms don't use coherent memory in BL1 unless 110 * cryptocell integration is enabled. 111 */ 112 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 113 #endif 114 115 const mmap_region_t bl_regions[] = { 116 MAP_BL1_TOTAL, 117 MAP_BL1_RO, 118 #if USE_ROMLIB 119 ARM_MAP_ROMLIB_CODE, 120 ARM_MAP_ROMLIB_DATA, 121 #endif 122 #if ARM_CRYPTOCELL_INTEG 123 ARM_MAP_BL_COHERENT_RAM, 124 #endif 125 {0} 126 }; 127 128 setup_page_tables(bl_regions, plat_arm_get_mmap()); 129 #ifdef AARCH32 130 enable_mmu_svc_mon(0); 131 #else 132 enable_mmu_el3(0); 133 #endif /* AARCH32 */ 134 135 arm_setup_romlib(); 136 } 137 138 void bl1_plat_arch_setup(void) 139 { 140 arm_bl1_plat_arch_setup(); 141 } 142 143 /* 144 * Perform the platform specific architecture setup shared between 145 * ARM standard platforms. 146 */ 147 void arm_bl1_platform_setup(void) 148 { 149 /* Initialise the IO layer and register platform IO devices */ 150 plat_arm_io_setup(); 151 arm_load_tb_fw_config(); 152 #if TRUSTED_BOARD_BOOT 153 /* Share the Mbed TLS heap info with other images */ 154 arm_bl1_set_mbedtls_heap(); 155 #endif /* TRUSTED_BOARD_BOOT */ 156 157 /* 158 * Allow access to the System counter timer module and program 159 * counter frequency for non secure images during FWU 160 */ 161 arm_configure_sys_timer(); 162 write_cntfrq_el0(plat_get_syscnt_freq2()); 163 } 164 165 void bl1_platform_setup(void) 166 { 167 arm_bl1_platform_setup(); 168 } 169 170 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 171 { 172 #if !ARM_DISABLE_TRUSTED_WDOG 173 /* Disable watchdog before leaving BL1 */ 174 sp805_stop(ARM_SP805_TWDG_BASE); 175 #endif 176 177 #ifdef EL3_PAYLOAD_BASE 178 /* 179 * Program the EL3 payload's entry point address into the CPUs mailbox 180 * in order to release secondary CPUs from their holding pen and make 181 * them jump there. 182 */ 183 plat_arm_program_trusted_mailbox(ep_info->pc); 184 dsbsy(); 185 sev(); 186 #endif 187 } 188 189 /* 190 * On Arm platforms, the FWU process is triggered when the FIP image has 191 * been tampered with. 192 */ 193 int plat_arm_bl1_fwu_needed(void) 194 { 195 return (arm_io_is_toc_valid() != 1); 196 } 197 198 /******************************************************************************* 199 * The following function checks if Firmware update is needed, 200 * by checking if TOC in FIP image is valid or not. 201 ******************************************************************************/ 202 unsigned int bl1_plat_get_next_image_id(void) 203 { 204 if (plat_arm_bl1_fwu_needed() != 0) 205 return NS_BL1U_IMAGE_ID; 206 207 return BL2_IMAGE_ID; 208 } 209