1*6ec0c65bSUsama Arif /* 2*6ec0c65bSUsama Arif * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*6ec0c65bSUsama Arif * 4*6ec0c65bSUsama Arif * SPDX-License-Identifier: BSD-3-Clause 5*6ec0c65bSUsama Arif */ 6*6ec0c65bSUsama Arif 7*6ec0c65bSUsama Arif #include <plat/arm/common/plat_arm.h> 8*6ec0c65bSUsama Arif #include <plat/arm/css/common/css_pm.h> 9*6ec0c65bSUsama Arif 10*6ec0c65bSUsama Arif /****************************************************************************** 11*6ec0c65bSUsama Arif * The power domain tree descriptor. 12*6ec0c65bSUsama Arif ******************************************************************************/ 13*6ec0c65bSUsama Arif const unsigned char tc_pd_tree_desc[] = { 14*6ec0c65bSUsama Arif PLAT_ARM_CLUSTER_COUNT, 15*6ec0c65bSUsama Arif PLAT_MAX_CPUS_PER_CLUSTER, 16*6ec0c65bSUsama Arif }; 17*6ec0c65bSUsama Arif 18*6ec0c65bSUsama Arif /******************************************************************************* 19*6ec0c65bSUsama Arif * This function returns the topology tree information. 20*6ec0c65bSUsama Arif ******************************************************************************/ 21*6ec0c65bSUsama Arif const unsigned char *plat_get_power_domain_tree_desc(void) 22*6ec0c65bSUsama Arif { 23*6ec0c65bSUsama Arif return tc_pd_tree_desc; 24*6ec0c65bSUsama Arif } 25*6ec0c65bSUsama Arif 26*6ec0c65bSUsama Arif /******************************************************************************* 27*6ec0c65bSUsama Arif * The array mapping platform core position (implemented by plat_my_core_pos()) 28*6ec0c65bSUsama Arif * to the SCMI power domain ID implemented by SCP. 29*6ec0c65bSUsama Arif ******************************************************************************/ 30*6ec0c65bSUsama Arif const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { 31*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), 32*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), 33*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), 34*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), 35*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)), 36*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)), 37*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)), 38*6ec0c65bSUsama Arif (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)), 39*6ec0c65bSUsama Arif }; 40*6ec0c65bSUsama Arif 41*6ec0c65bSUsama Arif /******************************************************************************* 42*6ec0c65bSUsama Arif * This function returns the core count within the cluster corresponding to 43*6ec0c65bSUsama Arif * `mpidr`. 44*6ec0c65bSUsama Arif ******************************************************************************/ 45*6ec0c65bSUsama Arif unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 46*6ec0c65bSUsama Arif { 47*6ec0c65bSUsama Arif return PLAT_MAX_CPUS_PER_CLUSTER; 48*6ec0c65bSUsama Arif } 49*6ec0c65bSUsama Arif 50*6ec0c65bSUsama Arif #if ARM_PLAT_MT 51*6ec0c65bSUsama Arif /****************************************************************************** 52*6ec0c65bSUsama Arif * Return the number of PE's supported by the CPU. 53*6ec0c65bSUsama Arif *****************************************************************************/ 54*6ec0c65bSUsama Arif unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr) 55*6ec0c65bSUsama Arif { 56*6ec0c65bSUsama Arif return PLAT_MAX_PE_PER_CPU; 57*6ec0c65bSUsama Arif } 58*6ec0c65bSUsama Arif #endif 59