1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <plat/common/platform.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/ccn.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 #include <drivers/arm/sbsa.h> 18 19 #if SPM_MM 20 #include <services/spm_mm_partition.h> 21 #endif 22 23 /* 24 * Table of regions for different BL stages to map using the MMU. 25 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 26 * arm_configure_mmu_elx() will give the available subset of that. 27 */ 28 #if IMAGE_BL1 29 const mmap_region_t plat_arm_mmap[] = { 30 ARM_MAP_SHARED_RAM, 31 TC_FLASH0_RO, 32 TC_MAP_DEVICE, 33 {0} 34 }; 35 #endif 36 #if IMAGE_BL2 37 const mmap_region_t plat_arm_mmap[] = { 38 ARM_MAP_SHARED_RAM, 39 TC_FLASH0_RO, 40 TC_MAP_DEVICE, 41 TC_MAP_NS_DRAM1, 42 #if defined(SPD_spmd) 43 TC_MAP_TZC_DRAM1, 44 #endif 45 #if ARM_BL31_IN_DRAM 46 ARM_MAP_BL31_SEC_DRAM, 47 #endif 48 #if SPM_MM 49 ARM_SP_IMAGE_MMAP, 50 #endif 51 #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 52 ARM_MAP_BL1_RW, 53 #endif 54 #ifdef SPD_opteed 55 ARM_MAP_OPTEE_CORE_MEM, 56 ARM_OPTEE_PAGEABLE_LOAD_MEM, 57 #endif 58 {0} 59 }; 60 #endif 61 #if IMAGE_BL31 62 const mmap_region_t plat_arm_mmap[] = { 63 ARM_MAP_SHARED_RAM, 64 V2M_MAP_IOFPGA, 65 TC_MAP_DEVICE, 66 #if SPM_MM 67 ARM_SPM_BUF_EL3_MMAP, 68 #endif 69 {0} 70 }; 71 72 #if SPM_MM && defined(IMAGE_BL31) 73 const mmap_region_t plat_arm_secure_partition_mmap[] = { 74 PLAT_ARM_SECURE_MAP_DEVICE, 75 ARM_SP_IMAGE_MMAP, 76 ARM_SP_IMAGE_NS_BUF_MMAP, 77 ARM_SP_CPER_BUF_MMAP, 78 ARM_SP_IMAGE_RW_MMAP, 79 ARM_SPM_BUF_EL0_MMAP, 80 {0} 81 }; 82 #endif /* SPM_MM && defined(IMAGE_BL31) */ 83 #endif 84 85 ARM_CASSERT_MMAP 86 87 #if SPM_MM && defined(IMAGE_BL31) 88 /* 89 * Boot information passed to a secure partition during initialisation. Linear 90 * indices in MP information will be filled at runtime. 91 */ 92 static spm_mm_mp_info_t sp_mp_info[] = { 93 [0] = {0x81000000, 0}, 94 [1] = {0x81000100, 0}, 95 [2] = {0x81000200, 0}, 96 [3] = {0x81000300, 0}, 97 [4] = {0x81010000, 0}, 98 [5] = {0x81010100, 0}, 99 [6] = {0x81010200, 0}, 100 [7] = {0x81010300, 0}, 101 }; 102 103 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 104 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 105 .h.version = VERSION_1, 106 .h.size = sizeof(spm_mm_boot_info_t), 107 .h.attr = 0, 108 .sp_mem_base = ARM_SP_IMAGE_BASE, 109 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 110 .sp_image_base = ARM_SP_IMAGE_BASE, 111 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 112 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 113 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 114 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 115 .sp_image_size = ARM_SP_IMAGE_SIZE, 116 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 117 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 118 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 119 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 120 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 121 .num_cpus = PLATFORM_CORE_COUNT, 122 .mp_info = &sp_mp_info[0], 123 }; 124 125 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 126 { 127 return plat_arm_secure_partition_mmap; 128 } 129 130 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 131 void *cookie) 132 { 133 return &plat_arm_secure_partition_boot_info; 134 } 135 #endif /* SPM_MM && defined(IMAGE_BL31) */ 136 137 #if TRUSTED_BOARD_BOOT 138 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 139 { 140 assert(heap_addr != NULL); 141 assert(heap_size != NULL); 142 143 return arm_get_mbedtls_heap(heap_addr, heap_size); 144 } 145 #endif 146 147 void plat_arm_secure_wdt_start(void) 148 { 149 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); 150 } 151 152 void plat_arm_secure_wdt_stop(void) 153 { 154 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); 155 } 156