1# Copyright (c) 2021-2024, Arm Limited. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6include common/fdt_wrappers.mk 7 8TARGET_FLAVOUR := fvp 9# DPU with SCMI may not necessarily work, so allow its independence 10TC_DPU_USE_SCMI_CLK := 1 11# SCMI power domain control enable 12TC_SCMI_PD_CTRL_EN := 1 13 14# System setup 15CSS_USE_SCMI_SDS_DRIVER := 1 16HW_ASSISTED_COHERENCY := 1 17USE_COHERENT_MEM := 0 18GIC_ENABLE_V4_EXTN := 1 19GICV3_SUPPORT_GIC600 := 1 20override NEED_BL2U := no 21override ARM_PLAT_MT := 1 22 23# CPU setup 24ARM_ARCH_MINOR := 7 25BRANCH_PROTECTION := 1 26ENABLE_FEAT_MPAM := 1 # default is 2, optimise 27ENABLE_SVE_FOR_NS := 2 # to show we use it 28ENABLE_SVE_FOR_SWD := 1 29ENABLE_SME_FOR_NS := 2 30ENABLE_SME2_FOR_NS := 2 31ENABLE_SME_FOR_SWD := 1 32ENABLE_TRBE_FOR_NS := 1 33ENABLE_SYS_REG_TRACE_FOR_NS := 1 34ENABLE_FEAT_AMU := 1 35ENABLE_AMU_FCONF := 1 36ENABLE_AMU_AUXILIARY_COUNTERS := 1 37ENABLE_MPMM := 1 38ENABLE_MPMM_FCONF := 1 39ENABLE_FEAT_MTE2 := 2 40ENABLE_SPE_FOR_NS := 3 41ENABLE_FEAT_TCR2 := 3 42 43CTX_INCLUDE_AARCH32_REGS := 0 44 45ifeq (${SPD},spmd) 46 SPMD_SPM_AT_SEL2 := 1 47 CTX_INCLUDE_PAUTH_REGS := 1 48endif 49 50# TC RESOLUTION - LIST OF VALID OPTIONS (this impacts only FVP) 51TC_RESOLUTION_OPTIONS := 640x480p60 \ 52 1920x1080p60 53# Set default to the 640x480p60 resolution mode 54TC_RESOLUTION ?= $(firstword $(TC_RESOLUTION_OPTIONS)) 55 56# Check resolution option for FVP 57ifneq ($(filter ${TARGET_FLAVOUR}, fvp),) 58ifeq ($(filter ${TC_RESOLUTION}, ${TC_RESOLUTION_OPTIONS}),) 59 $(error TC_RESOLUTION is ${TC_RESOLUTION}, it must be: ${TC_RESOLUTION_OPTIONS}) 60endif 61endif 62 63ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0) 64 $(error Platform ${PLAT}$(TARGET_PLATFORM) is no longer available.) 65endif 66 67ifneq ($(shell expr $(TARGET_PLATFORM) = 2), 0) 68 $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \ 69 Some of the features might not work as expected) 70endif 71 72ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0) 73 $(error TARGET_PLATFORM must be less than or equal to 4) 74endif 75 76ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),) 77 $(error TARGET_FLAVOUR must be fvp or fpga) 78endif 79 80# Support for loading FS Image to DRAM 81TC_FPGA_FS_IMG_IN_RAM := 0 82 83# Support Loading of FIP image to DRAM 84TC_FPGA_FIP_IMG_IN_RAM := 0 85 86# Use simple panel instead of vencoder with DPU 87TC_DPU_USE_SIMPLE_PANEL := 0 88 89$(eval $(call add_defines, \ 90 TARGET_PLATFORM \ 91 TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \ 92 TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \ 93 TC_DPU_USE_SCMI_CLK \ 94 TC_SCMI_PD_CTRL_EN \ 95 TC_FPGA_FS_IMG_IN_RAM \ 96 TC_FPGA_FIP_IMG_IN_RAM \ 97 TC_DPU_USE_SIMPLE_PANEL \ 98)) 99 100CSS_LOAD_SCP_IMAGES := 1 101 102# Save DSU PMU registers on cluster off and restore them on cluster on 103PRESERVE_DSU_PMU_REGS := 1 104 105# Specify MHU type based on platform 106ifneq ($(filter ${TARGET_PLATFORM}, 2),) 107 PLAT_MHU_VERSION := 2 108else 109 PLAT_MHU_VERSION := 3 110endif 111 112# Include GICv3 driver files 113include drivers/arm/gic/v3/gicv3.mk 114 115ENT_GIC_SOURCES := ${GICV3_SOURCES} \ 116 plat/common/plat_gicv3.c \ 117 plat/arm/common/arm_gicv3.c 118 119TC_BASE = plat/arm/board/tc 120 121PLAT_INCLUDES += -I${TC_BASE}/include/ \ 122 -I${TC_BASE}/fdts/ 123 124# CPU libraries for TARGET_PLATFORM=1 125ifeq (${TARGET_PLATFORM}, 1) 126TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ 127 lib/cpus/aarch64/cortex_a715.S \ 128 lib/cpus/aarch64/cortex_x3.S 129endif 130 131# CPU libraries for TARGET_PLATFORM=2 132ifeq (${TARGET_PLATFORM}, 2) 133ERRATA_A520_2938996 := 1 134ERRATA_X4_2726228 := 1 135 136TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ 137 lib/cpus/aarch64/cortex_a720.S \ 138 lib/cpus/aarch64/cortex_x4.S 139endif 140 141# CPU libraries for TARGET_PLATFORM=3 142ifeq (${TARGET_PLATFORM}, 3) 143ERRATA_A520_2938996 := 1 144 145TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ 146 lib/cpus/aarch64/cortex_a725.S \ 147 lib/cpus/aarch64/cortex_x925.S 148endif 149 150# CPU libraries for TARGET_PLATFORM=4 151ifeq (${TARGET_PLATFORM}, 4) 152TC_CPU_SOURCES += lib/cpus/aarch64/cortex_gelas.S \ 153 lib/cpus/aarch64/nevis.S \ 154 lib/cpus/aarch64/travis.S 155endif 156 157INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c \ 158 plat/arm/common/arm_ni.c 159 160PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \ 161 ${TC_BASE}/include/tc_helpers.S 162 163 164ifneq (${ENABLE_STACK_PROTECTOR},0) 165PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_stack_protector.c 166endif 167 168BL1_SOURCES += ${INTERCONNECT_SOURCES} \ 169 ${TC_CPU_SOURCES} \ 170 ${TC_BASE}/tc_trusted_boot.c \ 171 ${TC_BASE}/tc_bl1_setup.c \ 172 ${TC_BASE}/tc_err.c \ 173 drivers/arm/sbsa/sbsa.c 174 175BL2_SOURCES += ${TC_BASE}/tc_security.c \ 176 ${TC_BASE}/tc_err.c \ 177 ${TC_BASE}/tc_trusted_boot.c \ 178 ${TC_BASE}/tc_bl2_setup.c \ 179 lib/utils/mem_region.c \ 180 drivers/arm/tzc/tzc400.c \ 181 plat/arm/common/arm_nor_psci_mem_protect.c 182 183ifeq ($(shell test $(TARGET_PLATFORM) -le 2; echo $$?),0) 184BL2_SOURCES += plat/arm/common/arm_tzc400.c 185endif 186 187BL31_SOURCES += ${INTERCONNECT_SOURCES} \ 188 ${TC_CPU_SOURCES} \ 189 ${ENT_GIC_SOURCES} \ 190 ${TC_BASE}/tc_bl31_setup.c \ 191 ${TC_BASE}/tc_topology.c \ 192 lib/fconf/fconf.c \ 193 lib/fconf/fconf_dyn_cfg_getter.c \ 194 drivers/arm/css/dsu/dsu.c \ 195 drivers/cfi/v2m/v2m_flash.c \ 196 lib/utils/mem_region.c \ 197 plat/arm/common/arm_nor_psci_mem_protect.c \ 198 drivers/arm/sbsa/sbsa.c 199 200BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 201 202# Add the FDT_SOURCES and options for Dynamic Config 203FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \ 204 ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts \ 205 ${TC_BASE}/fdts/${PLAT}_nt_fw_config.dts 206FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 207TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 208FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 209 210# Add the FW_CONFIG to FIP and specify the same to certtool 211$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 212# Add the TB_FW_CONFIG to FIP and specify the same to certtool 213$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 214# Add the NT_FW_CONFIG to FIP and specify the same to certtool 215$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 216 217ifeq (${SPD},spmd) 218ifeq ($(ARM_SPMC_MANIFEST_DTS),) 219ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_test_manifest.dts 220endif 221 222FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 223TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 224 225# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 226$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG})) 227endif 228 229#Device tree 230TC_HW_CONFIG_DTS := fdts/${PLAT}${TARGET_PLATFORM}.dts 231TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 232FDT_SOURCES += ${TC_HW_CONFIG_DTS} 233$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))) 234 235# Add the HW_CONFIG to FIP and specify the same to certtool 236$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG})) 237 238$(info Including rse_comms.mk) 239include drivers/arm/rse/rse_comms.mk 240 241BL1_SOURCES += ${RSE_COMMS_SOURCES} 242BL2_SOURCES += ${RSE_COMMS_SOURCES} 243BL31_SOURCES += ${RSE_COMMS_SOURCES} 244 245# Include Measured Boot makefile before any Crypto library makefile. 246# Crypto library makefile may need default definitions of Measured Boot build 247# flags present in Measured Boot makefile. 248ifeq (${MEASURED_BOOT},1) 249 ifeq (${DICE_PROTECTION_ENVIRONMENT},1) 250 $(info Including qcbor.mk) 251 include drivers/measured_boot/rse/qcbor.mk 252 $(info Including dice_prot_env.mk) 253 include drivers/measured_boot/rse/dice_prot_env.mk 254 255 BL1_SOURCES += ${QCBOR_SOURCES} \ 256 ${DPE_SOURCES} \ 257 plat/arm/board/tc/tc_common_dpe.c \ 258 plat/arm/board/tc/tc_bl1_dpe.c \ 259 lib/psa/dice_protection_environment.c \ 260 drivers/arm/css/sds/sds.c \ 261 drivers/delay_timer/delay_timer.c \ 262 drivers/delay_timer/generic_delay_timer.c 263 264 BL2_SOURCES += ${QCBOR_SOURCES} \ 265 ${DPE_SOURCES} \ 266 plat/arm/board/tc/tc_common_dpe.c \ 267 plat/arm/board/tc/tc_bl2_dpe.c \ 268 lib/psa/dice_protection_environment.c 269 270 PLAT_INCLUDES += -I${QCBOR_INCLUDES} \ 271 -Iinclude/lib/dice 272 else 273 $(info Including rse_measured_boot.mk) 274 include drivers/measured_boot/rse/rse_measured_boot.mk 275 276 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} \ 277 plat/arm/board/tc/tc_common_measured_boot.c \ 278 plat/arm/board/tc/tc_bl1_measured_boot.c \ 279 lib/psa/measured_boot.c 280 281 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} \ 282 plat/arm/board/tc/tc_common_measured_boot.c \ 283 plat/arm/board/tc/tc_bl2_measured_boot.c \ 284 lib/psa/measured_boot.c 285 endif 286endif 287 288ifeq (${TRNG_SUPPORT},1) 289 BL31_SOURCES += plat/arm/board/tc/tc_trng.c 290endif 291 292ifneq (${PLATFORM_TEST},) 293 # Add this include as first, before arm_common.mk. This is necessary 294 # because arm_common.mk builds Mbed TLS, and platform_test.mk can 295 # change the list of Mbed TLS files that are to be compiled 296 # (LIBMBEDTLS_SRCS). 297 include plat/arm/board/tc/platform_test.mk 298endif 299 300 301include plat/arm/common/arm_common.mk 302include plat/arm/css/common/css_common.mk 303include plat/arm/board/common/board_common.mk 304