1# Copyright (c) 2021-2024, Arm Limited. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6include common/fdt_wrappers.mk 7 8TARGET_FLAVOUR := fvp 9# DPU with SCMI may not necessarily work, so allow its independence 10TC_DPU_USE_SCMI_CLK := 1 11# SCMI power domain control enable 12TC_SCMI_PD_CTRL_EN := 1 13 14# System setup 15CSS_USE_SCMI_SDS_DRIVER := 1 16HW_ASSISTED_COHERENCY := 1 17USE_COHERENT_MEM := 0 18GIC_ENABLE_V4_EXTN := 1 19GICV3_SUPPORT_GIC600 := 1 20override NEED_BL2U := no 21override ARM_PLAT_MT := 1 22 23# CPU setup 24ARM_ARCH_MINOR := 7 25BRANCH_PROTECTION := 1 26ENABLE_FEAT_MPAM := 1 # default is 2, optimise 27ENABLE_SVE_FOR_NS := 2 # to show we use it 28ENABLE_SVE_FOR_SWD := 1 29ENABLE_SME_FOR_NS := 2 30ENABLE_SME2_FOR_NS := 2 31ENABLE_SME_FOR_SWD := 1 32ENABLE_TRBE_FOR_NS := 1 33ENABLE_SYS_REG_TRACE_FOR_NS := 1 34ENABLE_FEAT_AMU := 1 35ENABLE_AMU_FCONF := 1 36ENABLE_AMU_AUXILIARY_COUNTERS := 1 37ENABLE_MPMM := 1 38ENABLE_MPMM_FCONF := 1 39ENABLE_FEAT_MTE2 := 2 40ENABLE_SPE_FOR_NS := 3 41ENABLE_FEAT_TCR2 := 3 42 43ifneq ($(filter ${TARGET_PLATFORM}, 3),) 44ENABLE_FEAT_RNG_TRAP := 0 45else 46ENABLE_FEAT_RNG_TRAP := 1 47endif 48 49CTX_INCLUDE_AARCH32_REGS := 0 50 51ifeq (${SPD},spmd) 52 SPMD_SPM_AT_SEL2 := 1 53 CTX_INCLUDE_PAUTH_REGS := 1 54endif 55 56TRNG_SUPPORT := 1 57 58# TC RESOLUTION - LIST OF VALID OPTIONS (this impacts only FVP) 59TC_RESOLUTION_OPTIONS := 640x480p60 \ 60 1920x1080p60 61# Set default to the 640x480p60 resolution mode 62TC_RESOLUTION ?= $(firstword $(TC_RESOLUTION_OPTIONS)) 63 64# Check resolution option for FVP 65ifneq ($(filter ${TARGET_FLAVOUR}, fvp),) 66ifeq ($(filter ${TC_RESOLUTION}, ${TC_RESOLUTION_OPTIONS}),) 67 $(error TC_RESOLUTION is ${TC_RESOLUTION}, it must be: ${TC_RESOLUTION_OPTIONS}) 68endif 69endif 70 71ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0) 72 $(error Platform ${PLAT}$(TARGET_PLATFORM) is no longer available.) 73endif 74 75ifneq ($(shell expr $(TARGET_PLATFORM) = 2), 0) 76 $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \ 77 Some of the features might not work as expected) 78endif 79 80ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0) 81 $(error TARGET_PLATFORM must be less than or equal to 4) 82endif 83 84ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),) 85 $(error TARGET_FLAVOUR must be fvp or fpga) 86endif 87 88# Support for loading FS Image to DRAM 89TC_FPGA_FS_IMG_IN_RAM := 0 90 91# Support Loading of FIP image to DRAM 92TC_FPGA_FIP_IMG_IN_RAM := 0 93 94# Use simple panel instead of vencoder with DPU 95TC_DPU_USE_SIMPLE_PANEL := 0 96 97$(eval $(call add_defines, \ 98 TARGET_PLATFORM \ 99 TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \ 100 TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \ 101 TC_DPU_USE_SCMI_CLK \ 102 TC_SCMI_PD_CTRL_EN \ 103 TC_FPGA_FS_IMG_IN_RAM \ 104 TC_FPGA_FIP_IMG_IN_RAM \ 105 TC_DPU_USE_SIMPLE_PANEL \ 106)) 107 108CSS_LOAD_SCP_IMAGES := 1 109 110# Save DSU PMU registers on cluster off and restore them on cluster on 111PRESERVE_DSU_PMU_REGS := 1 112 113# Specify MHU type based on platform 114ifneq ($(filter ${TARGET_PLATFORM}, 2),) 115 PLAT_MHU_VERSION := 2 116else 117 PLAT_MHU_VERSION := 3 118endif 119 120# Include GICv3 driver files 121include drivers/arm/gic/v3/gicv3.mk 122 123ENT_GIC_SOURCES := ${GICV3_SOURCES} \ 124 plat/common/plat_gicv3.c \ 125 plat/arm/common/arm_gicv3.c 126 127TC_BASE = plat/arm/board/tc 128 129PLAT_INCLUDES += -I${TC_BASE}/include/ \ 130 -I${TC_BASE}/fdts/ 131 132# CPU libraries for TARGET_PLATFORM=1 133ifeq (${TARGET_PLATFORM}, 1) 134TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ 135 lib/cpus/aarch64/cortex_a715.S \ 136 lib/cpus/aarch64/cortex_x3.S 137endif 138 139# CPU libraries for TARGET_PLATFORM=2 140ifeq (${TARGET_PLATFORM}, 2) 141ERRATA_A520_2938996 := 1 142ERRATA_X4_2726228 := 1 143 144TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ 145 lib/cpus/aarch64/cortex_a720.S \ 146 lib/cpus/aarch64/cortex_x4.S 147endif 148 149# CPU libraries for TARGET_PLATFORM=3 150ifeq (${TARGET_PLATFORM}, 3) 151ERRATA_A520_2938996 := 1 152 153TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ 154 lib/cpus/aarch64/cortex_a725.S \ 155 lib/cpus/aarch64/cortex_x925.S 156endif 157 158# CPU libraries for TARGET_PLATFORM=4 159ifeq (${TARGET_PLATFORM}, 4) 160TC_CPU_SOURCES += lib/cpus/aarch64/cortex_gelas.S \ 161 lib/cpus/aarch64/nevis.S \ 162 lib/cpus/aarch64/travis.S 163endif 164 165INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c \ 166 plat/arm/common/arm_ni.c 167 168PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \ 169 ${TC_BASE}/include/tc_helpers.S 170 171 172ifneq (${ENABLE_STACK_PROTECTOR},0) 173PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_stack_protector.c 174endif 175 176BL1_SOURCES += ${INTERCONNECT_SOURCES} \ 177 ${TC_CPU_SOURCES} \ 178 ${TC_BASE}/tc_trusted_boot.c \ 179 ${TC_BASE}/tc_bl1_setup.c \ 180 ${TC_BASE}/tc_err.c \ 181 drivers/arm/sbsa/sbsa.c 182 183BL2_SOURCES += ${TC_BASE}/tc_security.c \ 184 ${TC_BASE}/tc_err.c \ 185 ${TC_BASE}/tc_trusted_boot.c \ 186 ${TC_BASE}/tc_bl2_setup.c \ 187 lib/utils/mem_region.c \ 188 drivers/arm/tzc/tzc400.c \ 189 plat/arm/common/arm_nor_psci_mem_protect.c 190 191ifeq ($(shell test $(TARGET_PLATFORM) -le 2; echo $$?),0) 192BL2_SOURCES += plat/arm/common/arm_tzc400.c 193endif 194 195BL31_SOURCES += ${INTERCONNECT_SOURCES} \ 196 ${TC_CPU_SOURCES} \ 197 ${ENT_GIC_SOURCES} \ 198 ${TC_BASE}/tc_bl31_setup.c \ 199 ${TC_BASE}/tc_topology.c \ 200 lib/fconf/fconf.c \ 201 lib/fconf/fconf_dyn_cfg_getter.c \ 202 drivers/arm/css/dsu/dsu.c \ 203 drivers/cfi/v2m/v2m_flash.c \ 204 lib/utils/mem_region.c \ 205 plat/arm/common/arm_nor_psci_mem_protect.c \ 206 drivers/arm/sbsa/sbsa.c 207 208BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 209 210# Add the FDT_SOURCES and options for Dynamic Config 211FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \ 212 ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts \ 213 ${TC_BASE}/fdts/${PLAT}_nt_fw_config.dts 214FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 215TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 216FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 217 218# Add the FW_CONFIG to FIP and specify the same to certtool 219$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 220# Add the TB_FW_CONFIG to FIP and specify the same to certtool 221$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 222# Add the NT_FW_CONFIG to FIP and specify the same to certtool 223$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 224 225ifeq (${SPD},spmd) 226ifeq ($(ARM_SPMC_MANIFEST_DTS),) 227ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_test_manifest.dts 228endif 229 230FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 231TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 232 233# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 234$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG})) 235endif 236 237#Device tree 238TC_HW_CONFIG_DTS := fdts/${PLAT}${TARGET_PLATFORM}.dts 239TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 240FDT_SOURCES += ${TC_HW_CONFIG_DTS} 241$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))) 242 243# Add the HW_CONFIG to FIP and specify the same to certtool 244$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG})) 245 246$(info Including rse_comms.mk) 247include drivers/arm/rse/rse_comms.mk 248 249BL1_SOURCES += ${RSE_COMMS_SOURCES} 250BL2_SOURCES += ${RSE_COMMS_SOURCES} 251BL31_SOURCES += ${RSE_COMMS_SOURCES} \ 252 lib/psa/rse_platform.c 253 254# Include Measured Boot makefile before any Crypto library makefile. 255# Crypto library makefile may need default definitions of Measured Boot build 256# flags present in Measured Boot makefile. 257ifeq (${MEASURED_BOOT},1) 258 ifeq (${DICE_PROTECTION_ENVIRONMENT},1) 259 $(info Including qcbor.mk) 260 include drivers/measured_boot/rse/qcbor.mk 261 $(info Including dice_prot_env.mk) 262 include drivers/measured_boot/rse/dice_prot_env.mk 263 264 BL1_SOURCES += ${QCBOR_SOURCES} \ 265 ${DPE_SOURCES} \ 266 plat/arm/board/tc/tc_common_dpe.c \ 267 plat/arm/board/tc/tc_bl1_dpe.c \ 268 lib/psa/dice_protection_environment.c \ 269 drivers/arm/css/sds/sds.c \ 270 drivers/delay_timer/delay_timer.c \ 271 drivers/delay_timer/generic_delay_timer.c 272 273 BL2_SOURCES += ${QCBOR_SOURCES} \ 274 ${DPE_SOURCES} \ 275 plat/arm/board/tc/tc_common_dpe.c \ 276 plat/arm/board/tc/tc_bl2_dpe.c \ 277 lib/psa/dice_protection_environment.c 278 279 PLAT_INCLUDES += -I${QCBOR_INCLUDES} \ 280 -Iinclude/lib/dice 281 else 282 $(info Including rse_measured_boot.mk) 283 include drivers/measured_boot/rse/rse_measured_boot.mk 284 285 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} \ 286 plat/arm/board/tc/tc_common_measured_boot.c \ 287 plat/arm/board/tc/tc_bl1_measured_boot.c \ 288 lib/psa/measured_boot.c 289 290 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} \ 291 plat/arm/board/tc/tc_common_measured_boot.c \ 292 plat/arm/board/tc/tc_bl2_measured_boot.c \ 293 lib/psa/measured_boot.c 294 endif 295endif 296 297BL31_SOURCES += plat/arm/board/tc/tc_trng.c 298 299ifneq (${ENABLE_FEAT_RNG_TRAP},0) 300 BL31_SOURCES += plat/arm/board/tc/tc_rng_trap.c 301endif 302 303ifneq (${PLATFORM_TEST},) 304 # Add this include as first, before arm_common.mk. This is necessary 305 # because arm_common.mk builds Mbed TLS, and platform_test.mk can 306 # change the list of Mbed TLS files that are to be compiled 307 # (LIBMBEDTLS_SRCS). 308 include plat/arm/board/tc/platform_test.mk 309endif 310 311 312include plat/arm/common/arm_common.mk 313include plat/arm/css/common/css_common.mk 314include plat/arm/board/common/board_common.mk 315