16ec0c65bSUsama Arif/* 23960bcdaSJagdish Gediya * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved. 36ec0c65bSUsama Arif * 46ec0c65bSUsama Arif * SPDX-License-Identifier: BSD-3-Clause 56ec0c65bSUsama Arif */ 66ec0c65bSUsama Arif 76ec0c65bSUsama Arif#include <arch.h> 86ec0c65bSUsama Arif#include <asm_macros.S> 96ec0c65bSUsama Arif#include <platform_def.h> 106ec0c65bSUsama Arif#include <cpu_macros.S> 116ec0c65bSUsama Arif 12*de8b9cedSJagdish Gediya#define TC_HANDLER(rev) plat_reset_handler_tc##rev 13*de8b9cedSJagdish Gediya#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev) 14*de8b9cedSJagdish Gediya 156ec0c65bSUsama Arif .globl plat_arm_calc_core_pos 166ec0c65bSUsama Arif .globl plat_reset_handler 176ec0c65bSUsama Arif 186ec0c65bSUsama Arif /* --------------------------------------------------------------------- 196ec0c65bSUsama Arif * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 206ec0c65bSUsama Arif * 216ec0c65bSUsama Arif * Function to calculate the core position on TC. 226ec0c65bSUsama Arif * 236ec0c65bSUsama Arif * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) + 246ec0c65bSUsama Arif * (CPUId * PLAT_MAX_PE_PER_CPU) + 256ec0c65bSUsama Arif * ThreadId 266ec0c65bSUsama Arif * 276ec0c65bSUsama Arif * which can be simplified as: 286ec0c65bSUsama Arif * 296ec0c65bSUsama Arif * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU) 306ec0c65bSUsama Arif * + ThreadId 316ec0c65bSUsama Arif * --------------------------------------------------------------------- 326ec0c65bSUsama Arif */ 336ec0c65bSUsama Ariffunc plat_arm_calc_core_pos 346ec0c65bSUsama Arif /* 356ec0c65bSUsama Arif * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it 366ec0c65bSUsama Arif * look as if in a multi-threaded implementation. 376ec0c65bSUsama Arif */ 386ec0c65bSUsama Arif tst x0, #MPIDR_MT_MASK 396ec0c65bSUsama Arif lsl x3, x0, #MPIDR_AFFINITY_BITS 406ec0c65bSUsama Arif csel x3, x3, x0, eq 416ec0c65bSUsama Arif 426ec0c65bSUsama Arif /* Extract individual affinity fields from MPIDR */ 436ec0c65bSUsama Arif ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 446ec0c65bSUsama Arif ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 456ec0c65bSUsama Arif ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 466ec0c65bSUsama Arif 476ec0c65bSUsama Arif /* Compute linear position */ 486ec0c65bSUsama Arif mov x4, #PLAT_MAX_CPUS_PER_CLUSTER 496ec0c65bSUsama Arif madd x1, x2, x4, x1 506ec0c65bSUsama Arif mov x5, #PLAT_MAX_PE_PER_CPU 516ec0c65bSUsama Arif madd x0, x1, x5, x0 526ec0c65bSUsama Arif ret 536ec0c65bSUsama Arifendfunc plat_arm_calc_core_pos 546ec0c65bSUsama Arif 55*de8b9cedSJagdish Gediyafunc enable_dsu_pmu_el1_access 56*de8b9cedSJagdish Gediya sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN 57*de8b9cedSJagdish Gediya sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN 58*de8b9cedSJagdish Gediya ret 59*de8b9cedSJagdish Gediyaendfunc enable_dsu_pmu_el1_access 60*de8b9cedSJagdish Gediya 61*de8b9cedSJagdish Gediyafunc TC_HANDLER(2) 62*de8b9cedSJagdish Gediya ret 63*de8b9cedSJagdish Gediyaendfunc TC_HANDLER(2) 64*de8b9cedSJagdish Gediya 65*de8b9cedSJagdish Gediyafunc TC_HANDLER(3) 66*de8b9cedSJagdish Gediya mov x9, lr 67*de8b9cedSJagdish Gediya bl enable_dsu_pmu_el1_access 68*de8b9cedSJagdish Gediya mov lr, x9 69*de8b9cedSJagdish Gediya ret 70*de8b9cedSJagdish Gediyaendfunc TC_HANDLER(3) 71*de8b9cedSJagdish Gediya 726ec0c65bSUsama Arif /* ----------------------------------------------------- 736ec0c65bSUsama Arif * void plat_reset_handler(void); 746ec0c65bSUsama Arif * ----------------------------------------------------- 756ec0c65bSUsama Arif */ 766ec0c65bSUsama Ariffunc plat_reset_handler 77*de8b9cedSJagdish Gediya mov x8, lr 78*de8b9cedSJagdish Gediya bl PLAT_RESET_HANDLER(TARGET_PLATFORM) 79*de8b9cedSJagdish Gediya mov lr, x8 806ec0c65bSUsama Arif ret 816ec0c65bSUsama Arifendfunc plat_reset_handler 82