xref: /rk3399_ARM-atf/plat/arm/board/tc/include/tc_helpers.S (revision 7dae0451dda5074191c3ecfdec5eece768c28212)
16ec0c65bSUsama Arif/*
2f036ddafSManish V Badarkhe * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
36ec0c65bSUsama Arif *
46ec0c65bSUsama Arif * SPDX-License-Identifier: BSD-3-Clause
56ec0c65bSUsama Arif */
66ec0c65bSUsama Arif
76ec0c65bSUsama Arif#include <arch.h>
86ec0c65bSUsama Arif#include <asm_macros.S>
96ec0c65bSUsama Arif#include <platform_def.h>
106ec0c65bSUsama Arif#include <cpu_macros.S>
116ec0c65bSUsama Arif
12*7dae0451SMin Yao Ng#include <c1_pro.h>
137b41acafSJagdish Gediya
14de8b9cedSJagdish Gediya#define TC_HANDLER(rev)         plat_reset_handler_tc##rev
15de8b9cedSJagdish Gediya#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
16de8b9cedSJagdish Gediya
176ec0c65bSUsama Arif	.globl	plat_arm_calc_core_pos
186ec0c65bSUsama Arif	.globl	plat_reset_handler
196ec0c65bSUsama Arif
206ec0c65bSUsama Arif	/* ---------------------------------------------------------------------
216ec0c65bSUsama Arif	 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
226ec0c65bSUsama Arif	 *
236ec0c65bSUsama Arif	 * Function to calculate the core position on TC.
246ec0c65bSUsama Arif	 *
256ec0c65bSUsama Arif	 * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
266ec0c65bSUsama Arif	 * (CPUId * PLAT_MAX_PE_PER_CPU) +
276ec0c65bSUsama Arif	 * ThreadId
286ec0c65bSUsama Arif	 *
296ec0c65bSUsama Arif	 * which can be simplified as:
306ec0c65bSUsama Arif	 *
316ec0c65bSUsama Arif	 * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
326ec0c65bSUsama Arif	 * + ThreadId
336ec0c65bSUsama Arif	 * ---------------------------------------------------------------------
346ec0c65bSUsama Arif	 */
356ec0c65bSUsama Ariffunc plat_arm_calc_core_pos
366ec0c65bSUsama Arif	/*
376ec0c65bSUsama Arif	 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
386ec0c65bSUsama Arif	 * look as if in a multi-threaded implementation.
396ec0c65bSUsama Arif	 */
406ec0c65bSUsama Arif	tst	x0, #MPIDR_MT_MASK
416ec0c65bSUsama Arif	lsl	x3, x0, #MPIDR_AFFINITY_BITS
426ec0c65bSUsama Arif	csel	x3, x3, x0, eq
436ec0c65bSUsama Arif
446ec0c65bSUsama Arif	/* Extract individual affinity fields from MPIDR */
456ec0c65bSUsama Arif	ubfx	x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
466ec0c65bSUsama Arif	ubfx	x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
476ec0c65bSUsama Arif	ubfx	x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
486ec0c65bSUsama Arif
496ec0c65bSUsama Arif	/* Compute linear position */
506ec0c65bSUsama Arif	mov	x4, #PLAT_MAX_CPUS_PER_CLUSTER
516ec0c65bSUsama Arif	madd	x1, x2, x4, x1
526ec0c65bSUsama Arif	mov	x5, #PLAT_MAX_PE_PER_CPU
536ec0c65bSUsama Arif	madd	x0, x1, x5, x0
546ec0c65bSUsama Arif	ret
556ec0c65bSUsama Arifendfunc plat_arm_calc_core_pos
566ec0c65bSUsama Arif
57e1b76cb0SJagdish Gediyafunc mark_extllc_presence
58e1b76cb0SJagdish Gediya#ifdef MCN_CONFIG_ADDR
598f61c204SJagdish Gediya	mov_imm	x0, (MCN_CONFIG_ADDR(0))
60e1b76cb0SJagdish Gediya	ldr	w1, [x0]
61e1b76cb0SJagdish Gediya	ubfx	x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
62*7dae0451SMin Yao Ng	jump_if_cpu_midr C1_PRO_MIDR, ARM_C1_PRO
637b41acafSJagdish Gediya	sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, CPUECTLR_EL1_EXTLLC_BIT, 1
647b41acafSJagdish Gediya	ret
65*7dae0451SMin Yao NgARM_C1_PRO:
66*7dae0451SMin Yao Ng	sysreg_bitfield_insert_from_gpr C1_PRO_IMP_CPUECTLR_EL1, x1, C1_PRO_CPUECTLR2_EL1_EXTLLC_BIT, 1
67e1b76cb0SJagdish Gediya#endif
68e1b76cb0SJagdish Gediya	ret
69e1b76cb0SJagdish Gediyaendfunc mark_extllc_presence
70e1b76cb0SJagdish Gediya
71de8b9cedSJagdish Gediyafunc enable_dsu_pmu_el1_access
72de8b9cedSJagdish Gediya	sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN
73de8b9cedSJagdish Gediya	sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN
74de8b9cedSJagdish Gediya	ret
75de8b9cedSJagdish Gediyaendfunc enable_dsu_pmu_el1_access
76de8b9cedSJagdish Gediya
77de8b9cedSJagdish Gediyafunc TC_HANDLER(3)
78de8b9cedSJagdish Gediya	mov	x9, lr
79e1b76cb0SJagdish Gediya	bl	mark_extllc_presence
80de8b9cedSJagdish Gediya	bl	enable_dsu_pmu_el1_access
81de8b9cedSJagdish Gediya	mov	lr, x9
82de8b9cedSJagdish Gediya	ret
83de8b9cedSJagdish Gediyaendfunc TC_HANDLER(3)
84de8b9cedSJagdish Gediya
85e8e1b608SJackson Cooper-Driverfunc TC_HANDLER(4)
8600397b30SJagdish Gediya	mov	x9, lr
877b41acafSJagdish Gediya	bl	mark_extllc_presence
8800397b30SJagdish Gediya	bl	enable_dsu_pmu_el1_access
8900397b30SJagdish Gediya	mov	lr, x9
90e8e1b608SJackson Cooper-Driver	ret
91e8e1b608SJackson Cooper-Driverendfunc TC_HANDLER(4)
92e8e1b608SJackson Cooper-Driver
936ec0c65bSUsama Arif	/* -----------------------------------------------------
946ec0c65bSUsama Arif	 * void plat_reset_handler(void);
956ec0c65bSUsama Arif	 * -----------------------------------------------------
966ec0c65bSUsama Arif	 */
976ec0c65bSUsama Ariffunc plat_reset_handler
98de8b9cedSJagdish Gediya	mov	x8, lr
99de8b9cedSJagdish Gediya	bl	PLAT_RESET_HANDLER(TARGET_PLATFORM)
100de8b9cedSJagdish Gediya	mov	lr, x8
1016ec0c65bSUsama Arif	ret
1026ec0c65bSUsama Arifendfunc plat_reset_handler
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