1*6ec0c65bSUsama Arif/* 2*6ec0c65bSUsama Arif * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*6ec0c65bSUsama Arif * 4*6ec0c65bSUsama Arif * SPDX-License-Identifier: BSD-3-Clause 5*6ec0c65bSUsama Arif */ 6*6ec0c65bSUsama Arif 7*6ec0c65bSUsama Arif#include <arch.h> 8*6ec0c65bSUsama Arif#include <asm_macros.S> 9*6ec0c65bSUsama Arif#include <platform_def.h> 10*6ec0c65bSUsama Arif#include <cpu_macros.S> 11*6ec0c65bSUsama Arif 12*6ec0c65bSUsama Arif .globl plat_arm_calc_core_pos 13*6ec0c65bSUsama Arif .globl plat_reset_handler 14*6ec0c65bSUsama Arif 15*6ec0c65bSUsama Arif /* --------------------------------------------------------------------- 16*6ec0c65bSUsama Arif * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 17*6ec0c65bSUsama Arif * 18*6ec0c65bSUsama Arif * Function to calculate the core position on TC. 19*6ec0c65bSUsama Arif * 20*6ec0c65bSUsama Arif * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) + 21*6ec0c65bSUsama Arif * (CPUId * PLAT_MAX_PE_PER_CPU) + 22*6ec0c65bSUsama Arif * ThreadId 23*6ec0c65bSUsama Arif * 24*6ec0c65bSUsama Arif * which can be simplified as: 25*6ec0c65bSUsama Arif * 26*6ec0c65bSUsama Arif * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU) 27*6ec0c65bSUsama Arif * + ThreadId 28*6ec0c65bSUsama Arif * --------------------------------------------------------------------- 29*6ec0c65bSUsama Arif */ 30*6ec0c65bSUsama Ariffunc plat_arm_calc_core_pos 31*6ec0c65bSUsama Arif /* 32*6ec0c65bSUsama Arif * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it 33*6ec0c65bSUsama Arif * look as if in a multi-threaded implementation. 34*6ec0c65bSUsama Arif */ 35*6ec0c65bSUsama Arif tst x0, #MPIDR_MT_MASK 36*6ec0c65bSUsama Arif lsl x3, x0, #MPIDR_AFFINITY_BITS 37*6ec0c65bSUsama Arif csel x3, x3, x0, eq 38*6ec0c65bSUsama Arif 39*6ec0c65bSUsama Arif /* Extract individual affinity fields from MPIDR */ 40*6ec0c65bSUsama Arif ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 41*6ec0c65bSUsama Arif ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 42*6ec0c65bSUsama Arif ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 43*6ec0c65bSUsama Arif 44*6ec0c65bSUsama Arif /* Compute linear position */ 45*6ec0c65bSUsama Arif mov x4, #PLAT_MAX_CPUS_PER_CLUSTER 46*6ec0c65bSUsama Arif madd x1, x2, x4, x1 47*6ec0c65bSUsama Arif mov x5, #PLAT_MAX_PE_PER_CPU 48*6ec0c65bSUsama Arif madd x0, x1, x5, x0 49*6ec0c65bSUsama Arif ret 50*6ec0c65bSUsama Arifendfunc plat_arm_calc_core_pos 51*6ec0c65bSUsama Arif 52*6ec0c65bSUsama Arif /* ----------------------------------------------------- 53*6ec0c65bSUsama Arif * void plat_reset_handler(void); 54*6ec0c65bSUsama Arif * 55*6ec0c65bSUsama Arif * Determine the CPU MIDR and disable power down bit for 56*6ec0c65bSUsama Arif * that CPU. 57*6ec0c65bSUsama Arif * ----------------------------------------------------- 58*6ec0c65bSUsama Arif */ 59*6ec0c65bSUsama Ariffunc plat_reset_handler 60*6ec0c65bSUsama Arif ret 61*6ec0c65bSUsama Arifendfunc plat_reset_handler 62