1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <platform_def.h> 7 8/ { 9 compatible = "arm,ffa-core-manifest-1.0"; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 attribute { 14 spmc_id = <0x8000>; 15 maj_ver = <0x1>; 16 min_ver = <0x2>; 17 exec_state = <0x0>; 18 load_address = <0x0 0xfd000000>; 19 entrypoint = <0x0 0xfd000000>; 20 binary_size = <0x80000>; 21 }; 22 23 hafnium:hypervisor { 24 compatible = "hafnium,hafnium"; 25 /* filled in in top level .dts */ 26 }; 27 28 cpus { 29 #address-cells = <0x2>; 30 #size-cells = <0x0>; 31 32 CPU0:cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,armv8"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 }; 38 39 /* 40 * SPMC (Hafnium) requires secondary cpu nodes are declared in 41 * descending order 42 */ 43 CPU7:cpu@700 { 44 device_type = "cpu"; 45 compatible = "arm,armv8"; 46 reg = <0x0 0x700>; 47 enable-method = "psci"; 48 }; 49 50 CPU6:cpu@600 { 51 device_type = "cpu"; 52 compatible = "arm,armv8"; 53 reg = <0x0 0x600>; 54 enable-method = "psci"; 55 }; 56 57 CPU5:cpu@500 { 58 device_type = "cpu"; 59 compatible = "arm,armv8"; 60 reg = <0x0 0x500>; 61 enable-method = "psci"; 62 }; 63 64 CPU4:cpu@400 { 65 device_type = "cpu"; 66 compatible = "arm,armv8"; 67 reg = <0x0 0x400>; 68 enable-method = "psci"; 69 }; 70 71 CPU3:cpu@300 { 72 device_type = "cpu"; 73 compatible = "arm,armv8"; 74 reg = <0x0 0x300>; 75 enable-method = "psci"; 76 }; 77 78 CPU2:cpu@200 { 79 device_type = "cpu"; 80 compatible = "arm,armv8"; 81 reg = <0x0 0x200>; 82 enable-method = "psci"; 83 }; 84 85 CPU1:cpu@100 { 86 device_type = "cpu"; 87 compatible = "arm,armv8"; 88 reg = <0x0 0x100>; 89 enable-method = "psci"; 90 }; 91 }; 92 93 /* the full secure world range */ 94 memory@0 { 95 device_type = "memory"; 96 reg = <0x0 TC_TZC_DRAM1_BASE 0x0 TC_TZC_DRAM1_SIZE>, 97 <0x0 0xff000000 0x0 0x1000000>; 98 }; 99 100 memory@1 { 101 device_type = "ns-memory"; 102 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 103 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 104 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 105 }; 106 107 memory@2 { 108 device_type = "device-memory"; 109 reg = <0x0 0x25000000 0x0 0x10000>; /* For cactus tertiary dummy device. */ 110 }; 111 112 s_uart { 113 device_type = "device-memory"; 114 reg = <0x0 PLAT_ARM_BOOT_UART_BASE 0x0 0x01000>; 115 }; 116 117#ifdef TS_SP_FW_CONFIG 118 ns_flash { 119 device_type = "ns-device-memory"; 120 reg = <0x0 V2M_FLASH0_BASE 0x0 V2M_FLASH0_SIZE>; 121 }; 122#endif 123}; 124