1 /* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/arm/css/css_mhu_doorbell.h> 14 #include <drivers/arm/css/scmi.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/arm/css/common/css_pm.h> 18 #include <plat/common/platform.h> 19 20 #include <nrd_ras.h> 21 #include <nrd_variant.h> 22 23 nrd_platform_info_t nrd_plat_info; 24 25 static scmi_channel_plat_info_t sgi575_scmi_plat_info = { 26 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 27 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, 28 .db_preserve_mask = 0xfffffffe, 29 .db_modify_mask = 0x1, 30 .ring_doorbell = &mhu_ring_doorbell, 31 }; 32 33 static scmi_channel_plat_info_t plat_rd_scmi_info[] = { 34 { 35 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 36 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 37 .db_preserve_mask = 0xfffffffe, 38 .db_modify_mask = 0x1, 39 .ring_doorbell = &mhuv2_ring_doorbell, 40 }, 41 #if (NRD_CHIP_COUNT > 1) 42 { 43 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 44 NRD_REMOTE_CHIP_MEM_OFFSET(1), 45 .db_reg_addr = PLAT_CSS_MHU_BASE 46 + NRD_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0), 47 .db_preserve_mask = 0xfffffffe, 48 .db_modify_mask = 0x1, 49 .ring_doorbell = &mhuv2_ring_doorbell, 50 }, 51 #endif 52 #if (NRD_CHIP_COUNT > 2) 53 { 54 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 55 NRD_REMOTE_CHIP_MEM_OFFSET(2), 56 .db_reg_addr = PLAT_CSS_MHU_BASE + 57 NRD_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0), 58 .db_preserve_mask = 0xfffffffe, 59 .db_modify_mask = 0x1, 60 .ring_doorbell = &mhuv2_ring_doorbell, 61 }, 62 #endif 63 #if (NRD_CHIP_COUNT > 3) 64 { 65 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 66 NRD_REMOTE_CHIP_MEM_OFFSET(3), 67 .db_reg_addr = PLAT_CSS_MHU_BASE + 68 NRD_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0), 69 .db_preserve_mask = 0xfffffffe, 70 .db_modify_mask = 0x1, 71 .ring_doorbell = &mhuv2_ring_doorbell, 72 }, 73 #endif 74 }; 75 76 static scmi_channel_plat_info_t plat3_rd_scmi_info[] = { 77 { 78 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 79 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 80 .db_preserve_mask = 0xfffffffe, 81 .db_modify_mask = 0x1, 82 .ring_doorbell = &mhu_ring_doorbell, 83 }, 84 #if (NRD_CHIP_COUNT > 1) 85 { 86 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 87 NRD_REMOTE_CHIP_MEM_OFFSET(1), 88 .db_reg_addr = PLAT_CSS_MHU_BASE + 89 NRD_REMOTE_CHIP_MEM_OFFSET(1) + 90 MHU_V3_SENDER_REG_SET(0), 91 .db_preserve_mask = 0xfffffffe, 92 .db_modify_mask = 0x1, 93 .ring_doorbell = &mhu_ring_doorbell, 94 }, 95 #endif 96 #if (NRD_CHIP_COUNT > 2) 97 { 98 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 99 NRD_REMOTE_CHIP_MEM_OFFSET(2), 100 .db_reg_addr = PLAT_CSS_MHU_BASE + 101 NRD_REMOTE_CHIP_MEM_OFFSET(2) + 102 MHU_V3_SENDER_REG_SET(0), 103 .db_preserve_mask = 0xfffffffe, 104 .db_modify_mask = 0x1, 105 .ring_doorbell = &mhu_ring_doorbell, 106 }, 107 #endif 108 #if (NRD_CHIP_COUNT > 3) 109 { 110 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 111 NRD_REMOTE_CHIP_MEM_OFFSET(3), 112 .db_reg_addr = PLAT_CSS_MHU_BASE + 113 NRD_REMOTE_CHIP_MEM_OFFSET(3) + 114 MHU_V3_SENDER_REG_SET(0), 115 .db_preserve_mask = 0xfffffffe, 116 .db_modify_mask = 0x1, 117 .ring_doorbell = &mhu_ring_doorbell, 118 }, 119 #endif 120 }; 121 122 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id) 123 { 124 if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM || 125 nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM || 126 nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM || 127 nrd_plat_info.platform_id == RD_V2_SID_VER_PART_NUM || 128 nrd_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM || 129 nrd_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) { 130 if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info)) { 131 panic(); 132 } 133 return &plat_rd_scmi_info[channel_id]; 134 } else if (nrd_plat_info.platform_id == RD_V3_SID_VER_PART_NUM || 135 nrd_plat_info.platform_id == RD_V3_CFG1_SID_VER_PART_NUM || 136 nrd_plat_info.platform_id == RD_V3_CFG2_SID_VER_PART_NUM) { 137 if (channel_id >= ARRAY_SIZE(plat3_rd_scmi_info)) { 138 panic(); 139 } 140 return &plat3_rd_scmi_info[channel_id]; 141 } else if (nrd_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) { 142 return &sgi575_scmi_plat_info; 143 } else { 144 panic(); 145 } 146 } 147 148 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 149 u_register_t arg2, u_register_t arg3) 150 { 151 nrd_plat_info.platform_id = plat_arm_nrd_get_platform_id(); 152 nrd_plat_info.config_id = plat_arm_nrd_get_config_id(); 153 nrd_plat_info.multi_chip_mode = plat_arm_nrd_get_multi_chip_mode(); 154 155 /* Initialize generic timer */ 156 generic_delay_timer_init(); 157 158 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 159 } 160 161 /******************************************************************************* 162 * This function inserts platform information via device tree nodes as, 163 * system-id { 164 * platform-id = <0>; 165 * config-id = <0>; 166 * } 167 ******************************************************************************/ 168 #if RESET_TO_BL31 169 static int append_config_node(uintptr_t fdt_base_addr, uintptr_t fdt_base_size) 170 { 171 void *fdt; 172 int nodeoffset, err; 173 unsigned int platid = 0, platcfg = 0; 174 175 if (fdt_base_addr == 0) { 176 ERROR("NT_FW CONFIG base address is NULL\n"); 177 return -1; 178 } 179 180 fdt = (void *)fdt_base_addr; 181 182 /* Check the validity of the fdt */ 183 if (fdt_check_header(fdt) != 0) { 184 ERROR("Invalid NT_FW_CONFIG DTB passed\n"); 185 return -1; 186 } 187 188 nodeoffset = fdt_subnode_offset(fdt, 0, "system-id"); 189 if (nodeoffset < 0) { 190 ERROR("Failed to get system-id node offset\n"); 191 return -1; 192 } 193 194 platid = plat_arm_nrd_get_platform_id(); 195 err = fdt_setprop_u32(fdt, nodeoffset, "platform-id", platid); 196 if (err < 0) { 197 ERROR("Failed to set platform-id\n"); 198 return -1; 199 } 200 201 platcfg = plat_arm_nrd_get_config_id(); 202 err = fdt_setprop_u32(fdt, nodeoffset, "config-id", platcfg); 203 if (err < 0) { 204 ERROR("Failed to set config-id\n"); 205 return -1; 206 } 207 208 platcfg = plat_arm_nrd_get_multi_chip_mode(); 209 err = fdt_setprop_u32(fdt, nodeoffset, "multi-chip-mode", platcfg); 210 if (err < 0) { 211 ERROR("Failed to set multi-chip-mode\n"); 212 return -1; 213 } 214 215 flush_dcache_range((uintptr_t)fdt, fdt_base_size); 216 return 0; 217 } 218 #endif 219 220 void nrd_bl31_common_platform_setup(void) 221 { 222 223 arm_bl31_platform_setup(); 224 225 /* Configure the warm reboot SGI for primary core */ 226 css_setup_cpu_pwr_down_intr(); 227 228 #if CSS_SYSTEM_GRACEFUL_RESET 229 /* Register priority level handlers for reboot */ 230 ehf_register_priority_handler(PLAT_REBOOT_PRI, 231 css_reboot_interrupt_handler); 232 #endif 233 234 #if RESET_TO_BL31 235 int ret = append_config_node(NRD_CSS_BL31_PRELOAD_DTB_BASE, 236 NRD_CSS_BL31_PRELOAD_DTB_SIZE); 237 238 if (ret != 0) { 239 panic(); 240 } 241 #endif 242 } 243 244 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 245 { 246 /* 247 * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are 248 * supported. 249 */ 250 if (((nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) && 251 (nrd_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) { 252 ops->cpu_standby = NULL; 253 ops->system_off = NULL; 254 ops->system_reset = NULL; 255 ops->get_sys_suspend_power_state = NULL; 256 ops->pwr_domain_suspend = NULL; 257 ops->pwr_domain_suspend_finish = NULL; 258 } 259 260 return css_scmi_override_pm_ops(ops); 261 } 262