180d37c28SDeepak Pandey /* 2*f91a8e4cSManish Pandey * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 380d37c28SDeepak Pandey * 480d37c28SDeepak Pandey * SPDX-License-Identifier: BSD-3-Clause 580d37c28SDeepak Pandey */ 680d37c28SDeepak Pandey 7bd9344f6SAntonio Nino Diaz #include <plat/arm/common/plat_arm.h> 880d37c28SDeepak Pandey 980d37c28SDeepak Pandey /* Topology */ 1080d37c28SDeepak Pandey typedef struct n1sdp_topology { 1180d37c28SDeepak Pandey const unsigned char *power_tree; 1280d37c28SDeepak Pandey unsigned int plat_cluster_core_count; 1380d37c28SDeepak Pandey } n1sdp_topology_t; 1480d37c28SDeepak Pandey 1580d37c28SDeepak Pandey /* 1680d37c28SDeepak Pandey * The power domain tree descriptor. The cluster power domains are 1780d37c28SDeepak Pandey * arranged so that when the PSCI generic code creates the power domain tree, 1880d37c28SDeepak Pandey * the indices of the CPU power domain nodes it allocates match the linear 1980d37c28SDeepak Pandey * indices returned by plat_core_pos_by_mpidr(). 2080d37c28SDeepak Pandey */ 2180d37c28SDeepak Pandey const unsigned char n1sdp_pd_tree_desc[] = { 22*f91a8e4cSManish Pandey PLAT_N1SDP_CHIP_COUNT, 2380d37c28SDeepak Pandey PLAT_ARM_CLUSTER_COUNT, 24*f91a8e4cSManish Pandey PLAT_ARM_CLUSTER_COUNT, 25*f91a8e4cSManish Pandey N1SDP_MAX_CPUS_PER_CLUSTER, 26*f91a8e4cSManish Pandey N1SDP_MAX_CPUS_PER_CLUSTER, 2780d37c28SDeepak Pandey N1SDP_MAX_CPUS_PER_CLUSTER, 2880d37c28SDeepak Pandey N1SDP_MAX_CPUS_PER_CLUSTER 2980d37c28SDeepak Pandey }; 3080d37c28SDeepak Pandey 3180d37c28SDeepak Pandey /* Topology configuration for n1sdp */ 3280d37c28SDeepak Pandey const n1sdp_topology_t n1sdp_topology = { 3380d37c28SDeepak Pandey .power_tree = n1sdp_pd_tree_desc, 3480d37c28SDeepak Pandey .plat_cluster_core_count = N1SDP_MAX_CPUS_PER_CLUSTER 3580d37c28SDeepak Pandey }; 3680d37c28SDeepak Pandey 3780d37c28SDeepak Pandey /******************************************************************************* 3880d37c28SDeepak Pandey * This function returns the topology tree information. 3980d37c28SDeepak Pandey ******************************************************************************/ 4080d37c28SDeepak Pandey const unsigned char *plat_get_power_domain_tree_desc(void) 4180d37c28SDeepak Pandey { 4280d37c28SDeepak Pandey return n1sdp_topology.power_tree; 4380d37c28SDeepak Pandey } 4480d37c28SDeepak Pandey 4580d37c28SDeepak Pandey /******************************************************************************* 4680d37c28SDeepak Pandey * This function returns the core count within the cluster corresponding to 4780d37c28SDeepak Pandey * `mpidr`. 4880d37c28SDeepak Pandey ******************************************************************************/ 4980d37c28SDeepak Pandey unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 5080d37c28SDeepak Pandey { 5180d37c28SDeepak Pandey return n1sdp_topology.plat_cluster_core_count; 5280d37c28SDeepak Pandey } 5380d37c28SDeepak Pandey 5480d37c28SDeepak Pandey /******************************************************************************* 5580d37c28SDeepak Pandey * The array mapping platform core position (implemented by plat_my_core_pos()) 5680d37c28SDeepak Pandey * to the SCMI power domain ID implemented by SCP. 5780d37c28SDeepak Pandey ******************************************************************************/ 5880d37c28SDeepak Pandey const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { 59*f91a8e4cSManish Pandey 0, 1, 2, 3, 4, 5, 6, 7}; 60