1*80d37c28SDeepak Pandey /* 2*80d37c28SDeepak Pandey * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*80d37c28SDeepak Pandey * 4*80d37c28SDeepak Pandey * SPDX-License-Identifier: BSD-3-Clause 5*80d37c28SDeepak Pandey */ 6*80d37c28SDeepak Pandey 7*80d37c28SDeepak Pandey #include <plat_arm.h> 8*80d37c28SDeepak Pandey 9*80d37c28SDeepak Pandey /* Topology */ 10*80d37c28SDeepak Pandey typedef struct n1sdp_topology { 11*80d37c28SDeepak Pandey const unsigned char *power_tree; 12*80d37c28SDeepak Pandey unsigned int plat_cluster_core_count; 13*80d37c28SDeepak Pandey } n1sdp_topology_t; 14*80d37c28SDeepak Pandey 15*80d37c28SDeepak Pandey /* 16*80d37c28SDeepak Pandey * The power domain tree descriptor. The cluster power domains are 17*80d37c28SDeepak Pandey * arranged so that when the PSCI generic code creates the power domain tree, 18*80d37c28SDeepak Pandey * the indices of the CPU power domain nodes it allocates match the linear 19*80d37c28SDeepak Pandey * indices returned by plat_core_pos_by_mpidr(). 20*80d37c28SDeepak Pandey */ 21*80d37c28SDeepak Pandey const unsigned char n1sdp_pd_tree_desc[] = { 22*80d37c28SDeepak Pandey PLAT_ARM_CLUSTER_COUNT, 23*80d37c28SDeepak Pandey N1SDP_MAX_CPUS_PER_CLUSTER, 24*80d37c28SDeepak Pandey N1SDP_MAX_CPUS_PER_CLUSTER 25*80d37c28SDeepak Pandey }; 26*80d37c28SDeepak Pandey 27*80d37c28SDeepak Pandey /* Topology configuration for n1sdp */ 28*80d37c28SDeepak Pandey const n1sdp_topology_t n1sdp_topology = { 29*80d37c28SDeepak Pandey .power_tree = n1sdp_pd_tree_desc, 30*80d37c28SDeepak Pandey .plat_cluster_core_count = N1SDP_MAX_CPUS_PER_CLUSTER 31*80d37c28SDeepak Pandey }; 32*80d37c28SDeepak Pandey 33*80d37c28SDeepak Pandey /******************************************************************************* 34*80d37c28SDeepak Pandey * This function returns the topology tree information. 35*80d37c28SDeepak Pandey ******************************************************************************/ 36*80d37c28SDeepak Pandey const unsigned char *plat_get_power_domain_tree_desc(void) 37*80d37c28SDeepak Pandey { 38*80d37c28SDeepak Pandey return n1sdp_topology.power_tree; 39*80d37c28SDeepak Pandey } 40*80d37c28SDeepak Pandey 41*80d37c28SDeepak Pandey /******************************************************************************* 42*80d37c28SDeepak Pandey * This function returns the core count within the cluster corresponding to 43*80d37c28SDeepak Pandey * `mpidr`. 44*80d37c28SDeepak Pandey ******************************************************************************/ 45*80d37c28SDeepak Pandey unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 46*80d37c28SDeepak Pandey { 47*80d37c28SDeepak Pandey return n1sdp_topology.plat_cluster_core_count; 48*80d37c28SDeepak Pandey } 49*80d37c28SDeepak Pandey 50*80d37c28SDeepak Pandey /******************************************************************************* 51*80d37c28SDeepak Pandey * The array mapping platform core position (implemented by plat_my_core_pos()) 52*80d37c28SDeepak Pandey * to the SCMI power domain ID implemented by SCP. 53*80d37c28SDeepak Pandey ******************************************************************************/ 54*80d37c28SDeepak Pandey const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { 55*80d37c28SDeepak Pandey 0, 1, 2, 3}; 56