1*cf85030eSsahil /* 2*cf85030eSsahil * Copyright (c) 2022, Arm Limited. All rights reserved. 3*cf85030eSsahil * 4*cf85030eSsahil * SPDX-License-Identifier: BSD-3-Clause 5*cf85030eSsahil */ 6*cf85030eSsahil 7*cf85030eSsahil #include <arch_helpers.h> 8*cf85030eSsahil #include <common/debug.h> 9*cf85030eSsahil #include <common/desc_image_load.h> 10*cf85030eSsahil #include <drivers/arm/css/sds.h> 11*cf85030eSsahil #include <libfdt.h> 12*cf85030eSsahil #include <plat/common/platform.h> 13*cf85030eSsahil 14*cf85030eSsahil #include "n1sdp_def.h" 15*cf85030eSsahil #include <plat/arm/common/plat_arm.h> 16*cf85030eSsahil 17*cf85030eSsahil /* 18*cf85030eSsahil * Platform information structure stored in SDS. 19*cf85030eSsahil * This structure holds information about platform's DDR 20*cf85030eSsahil * size which will be used to zero out the memory before 21*cf85030eSsahil * enabling the ECC capability as well as information 22*cf85030eSsahil * about multichip setup 23*cf85030eSsahil * - multichip mode 24*cf85030eSsahil * - secondary_count 25*cf85030eSsahil * - Local DDR size in GB, DDR memory in master board 26*cf85030eSsahil * - Remote DDR size in GB, DDR memory in secondary board 27*cf85030eSsahil */ 28*cf85030eSsahil struct n1sdp_plat_info { 29*cf85030eSsahil bool multichip_mode; 30*cf85030eSsahil uint8_t secondary_count; 31*cf85030eSsahil uint8_t local_ddr_size; 32*cf85030eSsahil uint8_t remote_ddr_size; 33*cf85030eSsahil } __packed; 34*cf85030eSsahil 35*cf85030eSsahil /******************************************************************************* 36*cf85030eSsahil * This function inserts Platform information via device tree nodes as, 37*cf85030eSsahil * platform-info { 38*cf85030eSsahil * multichip-mode = <0x0>; 39*cf85030eSsahil * secondary-chip-count = <0x0>; 40*cf85030eSsahil * local-ddr-size = <0x0>; 41*cf85030eSsahil * remote-ddr-size = <0x0>; 42*cf85030eSsahil * }; 43*cf85030eSsahil ******************************************************************************/ 44*cf85030eSsahil static int plat_n1sdp_append_config_node(struct n1sdp_plat_info *plat_info) 45*cf85030eSsahil { 46*cf85030eSsahil bl_mem_params_node_t *mem_params; 47*cf85030eSsahil void *fdt; 48*cf85030eSsahil int nodeoffset, err; 49*cf85030eSsahil 50*cf85030eSsahil mem_params = get_bl_mem_params_node(NT_FW_CONFIG_ID); 51*cf85030eSsahil if (mem_params == NULL) { 52*cf85030eSsahil ERROR("NT_FW CONFIG base address is NULL\n"); 53*cf85030eSsahil return -1; 54*cf85030eSsahil } 55*cf85030eSsahil 56*cf85030eSsahil fdt = (void *)(mem_params->image_info.image_base); 57*cf85030eSsahil 58*cf85030eSsahil /* Check the validity of the fdt */ 59*cf85030eSsahil if (fdt_check_header(fdt) != 0) { 60*cf85030eSsahil ERROR("Invalid NT_FW_CONFIG DTB passed\n"); 61*cf85030eSsahil return -1; 62*cf85030eSsahil } 63*cf85030eSsahil 64*cf85030eSsahil nodeoffset = fdt_subnode_offset(fdt, 0, "platform-info"); 65*cf85030eSsahil if (nodeoffset < 0) { 66*cf85030eSsahil ERROR("NT_FW_CONFIG: Failed to get platform-info node offset\n"); 67*cf85030eSsahil return -1; 68*cf85030eSsahil } 69*cf85030eSsahil 70*cf85030eSsahil err = fdt_setprop_u32(fdt, nodeoffset, "multichip-mode", 71*cf85030eSsahil plat_info->multichip_mode); 72*cf85030eSsahil if (err < 0) { 73*cf85030eSsahil ERROR("NT_FW_CONFIG: Failed to set multichip-mode\n"); 74*cf85030eSsahil return -1; 75*cf85030eSsahil } 76*cf85030eSsahil 77*cf85030eSsahil err = fdt_setprop_u32(fdt, nodeoffset, "secondary-chip-count", 78*cf85030eSsahil plat_info->secondary_count); 79*cf85030eSsahil if (err < 0) { 80*cf85030eSsahil ERROR("NT_FW_CONFIG: Failed to set secondary-chip-count\n"); 81*cf85030eSsahil return -1; 82*cf85030eSsahil } 83*cf85030eSsahil 84*cf85030eSsahil err = fdt_setprop_u32(fdt, nodeoffset, "local-ddr-size", 85*cf85030eSsahil plat_info->local_ddr_size); 86*cf85030eSsahil if (err < 0) { 87*cf85030eSsahil ERROR("NT_FW_CONFIG: Failed to set local-ddr-size\n"); 88*cf85030eSsahil return -1; 89*cf85030eSsahil } 90*cf85030eSsahil 91*cf85030eSsahil err = fdt_setprop_u32(fdt, nodeoffset, "remote-ddr-size", 92*cf85030eSsahil plat_info->remote_ddr_size); 93*cf85030eSsahil if (err < 0) { 94*cf85030eSsahil ERROR("NT_FW_CONFIG: Failed to set remote-ddr-size\n"); 95*cf85030eSsahil return -1; 96*cf85030eSsahil } 97*cf85030eSsahil 98*cf85030eSsahil flush_dcache_range((uintptr_t)fdt, mem_params->image_info.image_size); 99*cf85030eSsahil 100*cf85030eSsahil return 0; 101*cf85030eSsahil } 102*cf85030eSsahil 103*cf85030eSsahil /******************************************************************************* 104*cf85030eSsahil * This function returns the list of executable images. 105*cf85030eSsahil ******************************************************************************/ 106*cf85030eSsahil bl_params_t *plat_get_next_bl_params(void) 107*cf85030eSsahil { 108*cf85030eSsahil int ret; 109*cf85030eSsahil struct n1sdp_plat_info plat_info; 110*cf85030eSsahil 111*cf85030eSsahil ret = sds_init(); 112*cf85030eSsahil if (ret != SDS_OK) { 113*cf85030eSsahil ERROR("SDS initialization failed. ret:%d\n", ret); 114*cf85030eSsahil panic(); 115*cf85030eSsahil } 116*cf85030eSsahil 117*cf85030eSsahil ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID, 118*cf85030eSsahil N1SDP_SDS_PLATFORM_INFO_OFFSET, 119*cf85030eSsahil &plat_info, 120*cf85030eSsahil N1SDP_SDS_PLATFORM_INFO_SIZE, 121*cf85030eSsahil SDS_ACCESS_MODE_NON_CACHED); 122*cf85030eSsahil if (ret != SDS_OK) { 123*cf85030eSsahil ERROR("Error getting platform info from SDS. ret:%d\n", ret); 124*cf85030eSsahil panic(); 125*cf85030eSsahil } 126*cf85030eSsahil 127*cf85030eSsahil /* Validate plat_info SDS */ 128*cf85030eSsahil if ((plat_info.local_ddr_size == 0U) 129*cf85030eSsahil || (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) 130*cf85030eSsahil || (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) 131*cf85030eSsahil || (plat_info.secondary_count > N1SDP_MAX_SECONDARY_COUNT) 132*cf85030eSsahil ){ 133*cf85030eSsahil ERROR("platform info SDS is corrupted\n"); 134*cf85030eSsahil panic(); 135*cf85030eSsahil } 136*cf85030eSsahil 137*cf85030eSsahil ret = plat_n1sdp_append_config_node(&plat_info); 138*cf85030eSsahil if (ret != 0) { 139*cf85030eSsahil panic(); 140*cf85030eSsahil } 141*cf85030eSsahil 142*cf85030eSsahil return arm_get_next_bl_params(); 143*cf85030eSsahil } 144