180d37c28SDeepak Pandey/* 2*da6d75a0SJohn Tsichritzis * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 380d37c28SDeepak Pandey * 480d37c28SDeepak Pandey * SPDX-License-Identifier: BSD-3-Clause 580d37c28SDeepak Pandey */ 680d37c28SDeepak Pandey 780d37c28SDeepak Pandey#include <arch.h> 880d37c28SDeepak Pandey#include <asm_macros.S> 9*da6d75a0SJohn Tsichritzis#include <neoverse_n1.h> 1080d37c28SDeepak Pandey#include <cpu_macros.S> 1180d37c28SDeepak Pandey#include <platform_def.h> 1280d37c28SDeepak Pandey 1380d37c28SDeepak Pandey .globl plat_arm_calc_core_pos 1480d37c28SDeepak Pandey .globl plat_reset_handler 1580d37c28SDeepak Pandey 1680d37c28SDeepak Pandey /* ----------------------------------------------------- 1780d37c28SDeepak Pandey * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 1880d37c28SDeepak Pandey * 1980d37c28SDeepak Pandey * Helper function to calculate the core position. 2080d37c28SDeepak Pandey * (ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) + 2180d37c28SDeepak Pandey * (CPUId * N1SDP_MAX_PE_PER_CPU) + 2280d37c28SDeepak Pandey * ThreadId 2380d37c28SDeepak Pandey * 2480d37c28SDeepak Pandey * which can be simplified as: 2580d37c28SDeepak Pandey * 2680d37c28SDeepak Pandey * ((ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * 2780d37c28SDeepak Pandey * N1SDP_MAX_PE_PER_CPU) + ThreadId 2880d37c28SDeepak Pandey * ------------------------------------------------------ 2980d37c28SDeepak Pandey */ 3080d37c28SDeepak Pandey 3180d37c28SDeepak Pandeyfunc plat_arm_calc_core_pos 3280d37c28SDeepak Pandey mov x3, x0 3380d37c28SDeepak Pandey 3480d37c28SDeepak Pandey /* 3580d37c28SDeepak Pandey * The MT bit in MPIDR is always set for n1sdp and the 3680d37c28SDeepak Pandey * affinity level 0 corresponds to thread affinity level. 3780d37c28SDeepak Pandey */ 3880d37c28SDeepak Pandey 3980d37c28SDeepak Pandey /* Extract individual affinity fields from MPIDR */ 4080d37c28SDeepak Pandey ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 4180d37c28SDeepak Pandey ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 4280d37c28SDeepak Pandey ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 4380d37c28SDeepak Pandey 4480d37c28SDeepak Pandey /* Compute linear position */ 4580d37c28SDeepak Pandey mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER 4680d37c28SDeepak Pandey madd x1, x2, x4, x1 4780d37c28SDeepak Pandey mov x5, #N1SDP_MAX_PE_PER_CPU 4880d37c28SDeepak Pandey madd x0, x1, x5, x0 4980d37c28SDeepak Pandey ret 5080d37c28SDeepak Pandeyendfunc plat_arm_calc_core_pos 5180d37c28SDeepak Pandey 5280d37c28SDeepak Pandey /* ----------------------------------------------------- 5380d37c28SDeepak Pandey * void plat_reset_handler(void); 5480d37c28SDeepak Pandey * 5580d37c28SDeepak Pandey * Determine the CPU MIDR and disable power down bit for 5680d37c28SDeepak Pandey * that CPU. 5780d37c28SDeepak Pandey * ----------------------------------------------------- 5880d37c28SDeepak Pandey */ 5980d37c28SDeepak Pandey 6080d37c28SDeepak Pandeyfunc plat_reset_handler 61*da6d75a0SJohn Tsichritzis jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 6280d37c28SDeepak Pandey ret 6380d37c28SDeepak Pandey 6480d37c28SDeepak Pandey /* ----------------------------------------------------- 6580d37c28SDeepak Pandey * Disable CPU power down bit in power control register 6680d37c28SDeepak Pandey * ----------------------------------------------------- 6780d37c28SDeepak Pandey */ 68*da6d75a0SJohn TsichritzisN1: 69*da6d75a0SJohn Tsichritzis mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 70*da6d75a0SJohn Tsichritzis bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 71*da6d75a0SJohn Tsichritzis msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 7280d37c28SDeepak Pandey isb 7380d37c28SDeepak Pandey ret 7480d37c28SDeepak Pandeyendfunc plat_reset_handler 75