1*80d37c28SDeepak Pandey/* 2*80d37c28SDeepak Pandey * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*80d37c28SDeepak Pandey * 4*80d37c28SDeepak Pandey * SPDX-License-Identifier: BSD-3-Clause 5*80d37c28SDeepak Pandey */ 6*80d37c28SDeepak Pandey 7*80d37c28SDeepak Pandey#include <arch.h> 8*80d37c28SDeepak Pandey#include <asm_macros.S> 9*80d37c28SDeepak Pandey#include <cortex_ares.h> 10*80d37c28SDeepak Pandey#include <cpu_macros.S> 11*80d37c28SDeepak Pandey#include <platform_def.h> 12*80d37c28SDeepak Pandey 13*80d37c28SDeepak Pandey .globl plat_arm_calc_core_pos 14*80d37c28SDeepak Pandey .globl plat_reset_handler 15*80d37c28SDeepak Pandey 16*80d37c28SDeepak Pandey /* ----------------------------------------------------- 17*80d37c28SDeepak Pandey * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 18*80d37c28SDeepak Pandey * 19*80d37c28SDeepak Pandey * Helper function to calculate the core position. 20*80d37c28SDeepak Pandey * (ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) + 21*80d37c28SDeepak Pandey * (CPUId * N1SDP_MAX_PE_PER_CPU) + 22*80d37c28SDeepak Pandey * ThreadId 23*80d37c28SDeepak Pandey * 24*80d37c28SDeepak Pandey * which can be simplified as: 25*80d37c28SDeepak Pandey * 26*80d37c28SDeepak Pandey * ((ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * 27*80d37c28SDeepak Pandey * N1SDP_MAX_PE_PER_CPU) + ThreadId 28*80d37c28SDeepak Pandey * ------------------------------------------------------ 29*80d37c28SDeepak Pandey */ 30*80d37c28SDeepak Pandey 31*80d37c28SDeepak Pandeyfunc plat_arm_calc_core_pos 32*80d37c28SDeepak Pandey mov x3, x0 33*80d37c28SDeepak Pandey 34*80d37c28SDeepak Pandey /* 35*80d37c28SDeepak Pandey * The MT bit in MPIDR is always set for n1sdp and the 36*80d37c28SDeepak Pandey * affinity level 0 corresponds to thread affinity level. 37*80d37c28SDeepak Pandey */ 38*80d37c28SDeepak Pandey 39*80d37c28SDeepak Pandey /* Extract individual affinity fields from MPIDR */ 40*80d37c28SDeepak Pandey ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 41*80d37c28SDeepak Pandey ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 42*80d37c28SDeepak Pandey ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 43*80d37c28SDeepak Pandey 44*80d37c28SDeepak Pandey /* Compute linear position */ 45*80d37c28SDeepak Pandey mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER 46*80d37c28SDeepak Pandey madd x1, x2, x4, x1 47*80d37c28SDeepak Pandey mov x5, #N1SDP_MAX_PE_PER_CPU 48*80d37c28SDeepak Pandey madd x0, x1, x5, x0 49*80d37c28SDeepak Pandey ret 50*80d37c28SDeepak Pandeyendfunc plat_arm_calc_core_pos 51*80d37c28SDeepak Pandey 52*80d37c28SDeepak Pandey /* ----------------------------------------------------- 53*80d37c28SDeepak Pandey * void plat_reset_handler(void); 54*80d37c28SDeepak Pandey * 55*80d37c28SDeepak Pandey * Determine the CPU MIDR and disable power down bit for 56*80d37c28SDeepak Pandey * that CPU. 57*80d37c28SDeepak Pandey * ----------------------------------------------------- 58*80d37c28SDeepak Pandey */ 59*80d37c28SDeepak Pandey 60*80d37c28SDeepak Pandeyfunc plat_reset_handler 61*80d37c28SDeepak Pandey jump_if_cpu_midr CORTEX_ARES_MIDR, ARES 62*80d37c28SDeepak Pandey ret 63*80d37c28SDeepak Pandey 64*80d37c28SDeepak Pandey /* ----------------------------------------------------- 65*80d37c28SDeepak Pandey * Disable CPU power down bit in power control register 66*80d37c28SDeepak Pandey * ----------------------------------------------------- 67*80d37c28SDeepak Pandey */ 68*80d37c28SDeepak PandeyARES: 69*80d37c28SDeepak Pandey mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 70*80d37c28SDeepak Pandey bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK 71*80d37c28SDeepak Pandey msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 72*80d37c28SDeepak Pandey isb 73*80d37c28SDeepak Pandey ret 74*80d37c28SDeepak Pandeyendfunc plat_reset_handler 75