1# 2# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 8 drivers/arm/gic/v2/gicv2_main.c \ 9 drivers/arm/gic/v2/gicv2_helpers.c \ 10 plat/common/plat_gicv2.c \ 11 plat/arm/common/arm_gicv2.c 12 13JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 14 plat/arm/common/arm_cci.c 15 16JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 17 plat/arm/board/juno/juno_security.c \ 18 plat/arm/board/juno/juno_trng.c \ 19 plat/arm/common/arm_tzc400.c 20 21ifneq (${ENABLE_STACK_PROTECTOR}, 0) 22JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 23endif 24 25# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 26# SCP during power management operations and for SCP RAM Firmware transfer. 27CSS_USE_SCMI_SDS_DRIVER := 1 28 29PLAT_INCLUDES := -Iplat/arm/board/juno/include 30 31PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 32 plat/arm/board/juno/juno_common.c 33 34# Flag to enable support for AArch32 state on JUNO 35JUNO_AARCH32_EL3_RUNTIME := 0 36$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 37$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 38 39# Flag to enable support for TZMP1 on JUNO 40JUNO_TZMP1 := 0 41$(eval $(call assert_boolean,JUNO_TZMP1)) 42ifeq (${JUNO_TZMP1}, 1) 43$(eval $(call add_define,JUNO_TZMP1)) 44endif 45 46ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 47# Include BL32 in FIP 48NEED_BL32 := yes 49# BL31 is not required 50override BL31_SOURCES = 51 52# The BL32 needs to be built separately invoking the AARCH32 compiler and 53# be specifed via `BL32` build option. 54 ifneq (${ARCH}, aarch32) 55 override BL32_SOURCES = 56 endif 57endif 58 59ifeq (${ARCH},aarch64) 60BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 61 lib/cpus/aarch64/cortex_a57.S \ 62 lib/cpus/aarch64/cortex_a72.S \ 63 plat/arm/board/juno/juno_err.c \ 64 plat/arm/board/juno/juno_bl1_setup.c \ 65 drivers/arm/sp805/sp805.c \ 66 ${JUNO_INTERCONNECT_SOURCES} \ 67 ${JUNO_SECURITY_SOURCES} 68 69BL2_SOURCES += drivers/arm/sp805/sp805.c \ 70 lib/utils/mem_region.c \ 71 plat/arm/board/juno/juno_err.c \ 72 plat/arm/board/juno/juno_bl2_setup.c \ 73 plat/arm/common/arm_nor_psci_mem_protect.c \ 74 ${JUNO_SECURITY_SOURCES} 75 76BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 77 78BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 79 lib/cpus/aarch64/cortex_a53.S \ 80 lib/cpus/aarch64/cortex_a57.S \ 81 lib/cpus/aarch64/cortex_a72.S \ 82 lib/utils/mem_region.c \ 83 plat/arm/board/juno/juno_pm.c \ 84 plat/arm/board/juno/juno_topology.c \ 85 plat/arm/common/arm_nor_psci_mem_protect.c \ 86 ${JUNO_GIC_SOURCES} \ 87 ${JUNO_INTERCONNECT_SOURCES} \ 88 ${JUNO_SECURITY_SOURCES} 89 90ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 91BL1_SOURCES += drivers/arm/css/sds/sds.c 92endif 93 94ifeq (${TRUSTED_BOARD_BOOT}, 1) 95BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 96BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 97endif 98 99endif 100 101ifneq (${RESET_TO_BL31},0) 102 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 103 Please set RESET_TO_BL31 to 0.") 104endif 105 106ifeq ($(USE_ROMLIB),1) 107all : bl1_romlib.bin 108endif 109 110bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin 111 @echo "Building combined BL1 and ROMLIB binary for Juno $@" 112 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 113 114# Errata workarounds for Cortex-A53: 115ERRATA_A53_819472 := 1 116ERRATA_A53_824069 := 1 117ERRATA_A53_826319 := 1 118ERRATA_A53_827319 := 1 119ERRATA_A53_835769 := 1 120ERRATA_A53_836870 := 1 121ERRATA_A53_843419 := 1 122ERRATA_A53_855873 := 1 123 124# Errata workarounds for Cortex-A57: 125ERRATA_A57_806969 := 0 126ERRATA_A57_813419 := 1 127ERRATA_A57_813420 := 1 128ERRATA_A57_814670 := 1 129ERRATA_A57_817169 := 1 130ERRATA_A57_826974 := 1 131ERRATA_A57_826977 := 1 132ERRATA_A57_828024 := 1 133ERRATA_A57_829520 := 1 134ERRATA_A57_833471 := 1 135ERRATA_A57_859972 := 0 136 137# Errata workarounds for Cortex-A72: 138ERRATA_A72_859971 := 0 139 140# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 141# power down sequence 142SKIP_A57_L1_FLUSH_PWR_DWN := 1 143 144# Do not enable SVE 145ENABLE_SVE_FOR_NS := 0 146 147# Enable the dynamic translation tables library. 148ifeq (${ARCH},aarch32) 149 ifeq (${RESET_TO_SP_MIN},1) 150 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 151 endif 152else 153 ifeq (${RESET_TO_BL31},1) 154 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 155 endif 156endif 157 158ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 159 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 160 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1 161 else 162 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1 163 endif 164endif 165 166# Add the FDT_SOURCES and options for Dynamic Config 167FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts 168TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 169 170# Add the TB_FW_CONFIG to FIP and specify the same to certtool 171$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) 172 173include plat/arm/board/common/board_common.mk 174include plat/arm/common/arm_common.mk 175include plat/arm/soc/common/soc_css.mk 176include plat/arm/css/common/css_common.mk 177