xref: /rk3399_ARM-atf/plat/arm/board/juno/platform.mk (revision c948f77136c42a92d0bb660543a3600c36dcf7f1)
1#
2# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7JUNO_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
8				drivers/arm/gic/v2/gicv2_main.c		\
9				drivers/arm/gic/v2/gicv2_helpers.c	\
10				plat/common/plat_gicv2.c		\
11				plat/arm/common/arm_gicv2.c
12
13JUNO_INTERCONNECT_SOURCES	:=	drivers/arm/cci/cci.c		\
14					plat/arm/common/arm_cci.c
15
16JUNO_SECURITY_SOURCES	:=	drivers/arm/tzc/tzc400.c		\
17				plat/arm/board/juno/juno_security.c	\
18				plat/arm/board/juno/juno_trng.c		\
19				plat/arm/common/arm_tzc400.c
20
21ifneq (${ENABLE_STACK_PROTECTOR}, 0)
22JUNO_SECURITY_SOURCES	+=	plat/arm/board/juno/juno_stack_protector.c
23endif
24
25# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
26# SCP during power management operations and for SCP RAM Firmware transfer.
27CSS_USE_SCMI_SDS_DRIVER		:=	1
28
29PLAT_INCLUDES		:=	-Iplat/arm/board/juno/include		\
30				-Iplat/arm/css/drivers/scmi		\
31				-Iplat/arm/css/drivers/sds
32
33PLAT_BL_COMMON_SOURCES	:=	plat/arm/board/juno/${ARCH}/juno_helpers.S \
34				plat/arm/board/juno/juno_common.c
35
36# Flag to enable support for AArch32 state on JUNO
37JUNO_AARCH32_EL3_RUNTIME	:=	0
38$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME))
39$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME))
40
41# Flag to enable support for TZMP1 on JUNO
42JUNO_TZMP1		:=	0
43$(eval $(call assert_boolean,JUNO_TZMP1))
44ifeq (${JUNO_TZMP1}, 1)
45$(eval $(call add_define,JUNO_TZMP1))
46endif
47
48ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1)
49# Include BL32 in FIP
50NEED_BL32		:= yes
51# BL31 is not required
52override BL31_SOURCES =
53
54# The BL32 needs to be built separately invoking the AARCH32 compiler and
55# be specifed via `BL32` build option.
56  ifneq (${ARCH}, aarch32)
57    override BL32_SOURCES =
58  endif
59endif
60
61ifeq (${ARCH},aarch64)
62BL1_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
63				lib/cpus/aarch64/cortex_a57.S		\
64				lib/cpus/aarch64/cortex_a72.S		\
65				plat/arm/board/juno/juno_err.c		\
66				plat/arm/board/juno/juno_bl1_setup.c	\
67				${JUNO_INTERCONNECT_SOURCES}		\
68				${JUNO_SECURITY_SOURCES}
69
70BL2_SOURCES		+=	lib/utils/mem_region.c			\
71				plat/arm/board/juno/juno_err.c		\
72				plat/arm/board/juno/juno_bl2_setup.c	\
73				plat/arm/common/arm_nor_psci_mem_protect.c \
74				${JUNO_SECURITY_SOURCES}
75
76BL2U_SOURCES		+=	${JUNO_SECURITY_SOURCES}
77
78BL31_SOURCES		+=	drivers/cfi/v2m/v2m_flash.c		\
79				lib/cpus/aarch64/cortex_a53.S		\
80				lib/cpus/aarch64/cortex_a57.S		\
81				lib/cpus/aarch64/cortex_a72.S		\
82				lib/utils/mem_region.c			\
83				plat/arm/board/juno/juno_pm.c		\
84				plat/arm/board/juno/juno_topology.c	\
85				plat/arm/common/arm_nor_psci_mem_protect.c \
86				${JUNO_GIC_SOURCES}			\
87				${JUNO_INTERCONNECT_SOURCES}		\
88				${JUNO_SECURITY_SOURCES}
89
90ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
91BL1_SOURCES		+=	plat/arm/css/drivers/sds/sds.c
92endif
93
94endif
95
96ifneq (${RESET_TO_BL31},0)
97  $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
98  Please set RESET_TO_BL31 to 0.")
99endif
100
101ifeq ($(USE_ROMLIB),1)
102all : bl1_romlib.bin
103endif
104
105bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin
106	@echo "Building combined BL1 and ROMLIB binary for Juno $@"
107	./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT)
108
109# Errata workarounds for Cortex-A53:
110ERRATA_A53_826319		:=	1
111ERRATA_A53_835769		:=	1
112ERRATA_A53_836870		:=	1
113ERRATA_A53_843419		:=	1
114ERRATA_A53_855873		:=	1
115
116# Errata workarounds for Cortex-A57:
117ERRATA_A57_806969		:=	0
118ERRATA_A57_813419		:=	1
119ERRATA_A57_813420		:=	1
120ERRATA_A57_826974		:=	1
121ERRATA_A57_826977		:=	1
122ERRATA_A57_828024		:=	1
123ERRATA_A57_829520		:=	1
124ERRATA_A57_833471		:=	1
125ERRATA_A57_859972		:=	0
126
127# Errata workarounds for Cortex-A72:
128ERRATA_A72_859971		:=	0
129
130# Enable option to skip L1 data cache flush during the Cortex-A57 cluster
131# power down sequence
132SKIP_A57_L1_FLUSH_PWR_DWN	:=	 1
133
134# Do not enable SVE
135ENABLE_SVE_FOR_NS		:=	0
136
137include plat/arm/board/common/board_common.mk
138include plat/arm/common/arm_common.mk
139include plat/arm/soc/common/soc_css.mk
140include plat/arm/css/common/css_common.mk
141
142