1# 2# Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Include GICv2 driver files 10include drivers/arm/gic/v2/gicv2.mk 11 12JUNO_GIC_SOURCES := ${GICV2_SOURCES} \ 13 plat/common/plat_gicv2.c \ 14 plat/arm/common/arm_gicv2.c 15 16JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 17 plat/arm/common/arm_cci.c 18 19JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 20 plat/arm/board/juno/juno_security.c \ 21 plat/arm/board/juno/juno_trng.c \ 22 plat/arm/common/arm_tzc400.c 23 24ifneq (${ENABLE_STACK_PROTECTOR}, 0) 25JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 26endif 27 28# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 29# SCP during power management operations and for SCP RAM Firmware transfer. 30CSS_USE_SCMI_SDS_DRIVER := 1 31 32PLAT_INCLUDES := -Iplat/arm/board/juno/include 33 34PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 35 plat/arm/board/juno/juno_common.c 36 37# Flag to enable support for AArch32 state on JUNO 38JUNO_AARCH32_EL3_RUNTIME := 0 39$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 40$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 41 42# Flag to enable support for TZMP1 on JUNO 43JUNO_TZMP1 := 0 44$(eval $(call assert_boolean,JUNO_TZMP1)) 45ifeq (${JUNO_TZMP1}, 1) 46 ifeq (${ARM_ETHOSN_NPU_TZMP1},1) 47 $(error JUNO_TZMP1 cannot be used together with ARM_ETHOSN_NPU_TZMP1) 48 else 49 $(eval $(call add_define,JUNO_TZMP1)) 50 endif 51endif 52 53TRNG_SUPPORT := 1 54 55ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 56# Include BL32 in FIP 57NEED_BL32 := yes 58# BL31 is not required 59override BL31_SOURCES = 60 61# The BL32 needs to be built separately invoking the AARCH32 compiler and 62# be specifed via `BL32` build option. 63 ifneq (${ARCH}, aarch32) 64 override BL32_SOURCES = 65 endif 66endif 67 68ifeq (${ARCH},aarch64) 69BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 70 lib/cpus/aarch64/cortex_a57.S \ 71 lib/cpus/aarch64/cortex_a72.S \ 72 plat/arm/board/juno/juno_err.c \ 73 plat/arm/board/juno/juno_bl1_setup.c \ 74 drivers/arm/sp805/sp805.c \ 75 ${JUNO_INTERCONNECT_SOURCES} \ 76 ${JUNO_SECURITY_SOURCES} 77 78BL2_SOURCES += drivers/arm/sp805/sp805.c \ 79 lib/utils/mem_region.c \ 80 plat/arm/board/juno/juno_err.c \ 81 plat/arm/board/juno/juno_bl2_setup.c \ 82 plat/arm/common/arm_nor_psci_mem_protect.c \ 83 ${JUNO_SECURITY_SOURCES} 84 85BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 86 87BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 88 lib/cpus/aarch64/cortex_a53.S \ 89 lib/cpus/aarch64/cortex_a57.S \ 90 lib/cpus/aarch64/cortex_a72.S \ 91 lib/utils/mem_region.c \ 92 lib/fconf/fconf.c \ 93 lib/fconf/fconf_dyn_cfg_getter.c \ 94 plat/arm/board/juno/juno_bl31_setup.c \ 95 plat/arm/board/juno/juno_pm.c \ 96 plat/arm/board/juno/juno_topology.c \ 97 plat/arm/common/arm_nor_psci_mem_protect.c \ 98 ${JUNO_GIC_SOURCES} \ 99 ${JUNO_INTERCONNECT_SOURCES} \ 100 ${JUNO_SECURITY_SOURCES} 101 102BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 103 104ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 105BL1_SOURCES += drivers/arm/css/sds/sds.c 106endif 107 108ifeq (${TRUSTED_BOARD_BOOT}, 1) 109 # Enable Juno specific TBBR images 110 $(eval $(call add_define,PLAT_TBBR_IMG_DEF)) 111 DTC_CPPFLAGS += ${PLAT_INCLUDES} 112 113 BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 114 BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 115 116 ifeq (${COT_DESC_IN_DTB},0) 117 BL2_SOURCES += plat/arm/board/juno/juno_tbbr_cot_bl2.c 118 endif 119endif 120 121endif 122 123ifneq (${RESET_TO_BL31},0) 124 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 125 Please set RESET_TO_BL31 to 0.") 126endif 127 128ifeq ($(USE_ROMLIB),1) 129all : bl1_romlib.bin 130endif 131 132bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin romlib.bin 133 @echo "Building combined BL1 and ROMLIB binary for Juno $@" 134 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 135 136# Errata workarounds for Cortex-A53: 137ERRATA_A53_819472 := 1 138ERRATA_A53_824069 := 1 139ERRATA_A53_826319 := 1 140ERRATA_A53_827319 := 1 141ERRATA_A53_835769 := 1 142ERRATA_A53_836870 := 1 143ERRATA_A53_843419 := 1 144ERRATA_A53_855873 := 1 145 146# Errata workarounds for Cortex-A57: 147ERRATA_A57_806969 := 0 148ERRATA_A57_813419 := 1 149ERRATA_A57_813420 := 1 150ERRATA_A57_814670 := 1 151ERRATA_A57_817169 := 1 152ERRATA_A57_826974 := 1 153ERRATA_A57_826977 := 1 154ERRATA_A57_828024 := 1 155ERRATA_A57_829520 := 1 156ERRATA_A57_833471 := 1 157ERRATA_A57_859972 := 0 158 159# Errata workarounds for Cortex-A72: 160ERRATA_A72_859971 := 0 161 162# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 163# power down sequence 164SKIP_A57_L1_FLUSH_PWR_DWN := 1 165 166# Do not enable SVE 167ENABLE_SVE_FOR_NS := 0 168 169# Enable the dynamic translation tables library. 170ifeq (${ARCH},aarch32) 171 ifeq (${RESET_TO_SP_MIN},1) 172 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 173 endif 174else 175 ifeq (${RESET_TO_BL31},1) 176 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 177 endif 178endif 179 180ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 181 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 182 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 183 else 184 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 185 endif 186endif 187 188BL1_CPPFLAGS += -march=armv8-a+crc 189BL2_CPPFLAGS += -march=armv8-a+crc 190BL2U_CPPFLAGS += -march=armv8-a+crc 191BL31_CPPFLAGS += -march=armv8-a+crc 192BL32_CPPFLAGS += -march=armv8-a+crc 193 194# Add the FDT_SOURCES and options for Dynamic Config 195FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 196 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \ 197 fdts/${PLAT}.dts 198 199FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 200TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 201HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 202 203# Add the FW_CONFIG to FIP and specify the same to certtool 204$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 205# Add the TB_FW_CONFIG to FIP and specify the same to certtool 206$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 207# Add the HW_CONFIG to FIP and specify the same to certtool 208$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 209 210include plat/arm/board/common/board_common.mk 211include plat/arm/common/arm_common.mk 212include plat/arm/soc/common/soc_css.mk 213include plat/arm/css/common/css_common.mk 214