1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9USE_GIC_DRIVER := 2 10 11JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 12 plat/arm/common/arm_cci.c 13 14JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 15 plat/arm/board/juno/juno_security.c \ 16 plat/arm/board/juno/juno_trng.c \ 17 plat/arm/common/arm_tzc400.c 18 19ifneq (${ENABLE_STACK_PROTECTOR}, 0) 20JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 21endif 22 23# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 24# SCP during power management operations and for SCP RAM Firmware transfer. 25CSS_USE_SCMI_SDS_DRIVER := 1 26 27PLAT_INCLUDES := -Iplat/arm/board/juno/include 28 29PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 30 plat/arm/board/juno/juno_common.c 31 32ifeq (${SPMC_AT_EL3}, 1) 33PLAT_BL_COMMON_SOURCES += plat/arm/board/juno/juno_el3_spmc.c 34endif 35 36ifeq (${HOB_LIST}, 1) 37include lib/hob/hob.mk 38endif 39 40# Flag to enable support for AArch32 state on JUNO 41JUNO_AARCH32_EL3_RUNTIME := 0 42$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 43$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 44 45# Flag to enable support for TZMP1 on JUNO 46JUNO_TZMP1 := 0 47$(eval $(call assert_boolean,JUNO_TZMP1)) 48ifeq (${JUNO_TZMP1}, 1) 49 ifeq (${ETHOSN_NPU_TZMP1},1) 50 $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1) 51 else 52 $(eval $(call add_define,JUNO_TZMP1)) 53 endif 54endif 55 56TRNG_SUPPORT := 1 57 58ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 59# Include BL32 in FIP 60NEED_BL32 := yes 61# BL31 is not required 62override BL31_SOURCES = 63 64# The BL32 needs to be built separately invoking the AARCH32 compiler and 65# be specifed via `BL32` build option. 66 ifneq (${ARCH}, aarch32) 67 override BL32_SOURCES = 68 endif 69else 70 ifeq (${ARCH}, aarch32) 71 $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32) 72 endif 73endif 74 75ifeq (${ARCH},aarch64) 76BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 77 lib/cpus/aarch64/cortex_a57.S \ 78 lib/cpus/aarch64/cortex_a72.S \ 79 plat/arm/board/juno/juno_err.c \ 80 plat/arm/board/juno/juno_bl1_setup.c \ 81 drivers/arm/sp805/sp805.c \ 82 ${JUNO_INTERCONNECT_SOURCES} \ 83 ${JUNO_SECURITY_SOURCES} 84 85BL2_SOURCES += drivers/arm/sp805/sp805.c \ 86 lib/utils/mem_region.c \ 87 plat/arm/board/juno/juno_err.c \ 88 plat/arm/board/juno/juno_bl2_setup.c \ 89 plat/arm/common/arm_nor_psci_mem_protect.c \ 90 ${JUNO_SECURITY_SOURCES} 91 92BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 93 94BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 95 lib/cpus/aarch64/cortex_a53.S \ 96 lib/cpus/aarch64/cortex_a57.S \ 97 lib/cpus/aarch64/cortex_a72.S \ 98 lib/utils/mem_region.c \ 99 lib/fconf/fconf.c \ 100 lib/fconf/fconf_dyn_cfg_getter.c \ 101 plat/arm/board/juno/juno_bl31_setup.c \ 102 plat/arm/board/juno/juno_pm.c \ 103 plat/arm/board/juno/juno_topology.c \ 104 plat/arm/common/arm_nor_psci_mem_protect.c \ 105 ${JUNO_INTERCONNECT_SOURCES} \ 106 ${JUNO_SECURITY_SOURCES} 107 108BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 109 110ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 111BL1_SOURCES += drivers/arm/css/sds/sds.c 112endif 113 114ifeq (${TRUSTED_BOARD_BOOT}, 1) 115 # Enable Juno specific TBBR images 116 $(eval $(call add_define,PLAT_TBBR_IMG_DEF)) 117 DTC_CPPFLAGS += ${PLAT_INCLUDES} 118 119 BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 120 BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 121 122 ifeq (${COT_DESC_IN_DTB},0) 123 BL2_SOURCES += plat/arm/board/juno/juno_tbbr_cot_bl2.c 124 endif 125endif 126 127endif 128 129ifneq (${RESET_TO_BL31},0) 130 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 131 Please set RESET_TO_BL31 to 0.") 132endif 133 134ifeq ($(USE_ROMLIB),1) 135all: $(BUILD_PLAT)/bl1_romlib.bin 136endif 137 138$(BUILD_PLAT)/bl1_romlib.bin: $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin 139 $(s)echo "Building combined BL1 and ROMLIB binary for Juno $@" 140 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 141 142# Errata workarounds for Cortex-A53: 143ERRATA_A53_819472 := 1 144ERRATA_A53_824069 := 1 145ERRATA_A53_826319 := 1 146ERRATA_A53_827319 := 1 147ERRATA_A53_835769 := 1 148ERRATA_A53_836870 := 1 149ERRATA_A53_843419 := 1 150ERRATA_A53_855873 := 1 151 152# Errata workarounds for Cortex-A57: 153ERRATA_A57_806969 := 0 154ERRATA_A57_813419 := 1 155ERRATA_A57_813420 := 1 156ERRATA_A57_814670 := 1 157ERRATA_A57_817169 := 1 158ERRATA_A57_826974 := 1 159ERRATA_A57_826977 := 1 160ERRATA_A57_828024 := 1 161ERRATA_A57_829520 := 1 162ERRATA_A57_833471 := 1 163ERRATA_A57_859972 := 0 164 165# Errata workarounds for Cortex-A72: 166ERRATA_A72_859971 := 0 167 168# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 169# power down sequence 170SKIP_A57_L1_FLUSH_PWR_DWN := 1 171 172# Do not enable SVE 173ENABLE_SVE_FOR_NS := 0 174 175# Enable the dynamic translation tables library. 176ifeq (${ARCH},aarch32) 177 ifeq (${RESET_TO_SP_MIN},1) 178 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 179 endif 180else 181 ifeq (${RESET_TO_BL31},1) 182 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 183 endif 184endif 185 186ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 187 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 188 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 189 else 190 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 191 endif 192endif 193 194BL1_CPPFLAGS += -march=armv8-a+crc 195BL2_CPPFLAGS += -march=armv8-a+crc 196BL2U_CPPFLAGS += -march=armv8-a+crc 197BL31_CPPFLAGS += -march=armv8-a+crc 198BL32_CPPFLAGS += -march=armv8-a+crc 199 200# Add the FDT_SOURCES and options for Dynamic Config 201FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 202 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \ 203 fdts/${PLAT}.dts 204 205FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 206TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 207HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 208 209# Add the FW_CONFIG to FIP and specify the same to certtool 210$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 211# Add the TB_FW_CONFIG to FIP and specify the same to certtool 212$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 213# Add the HW_CONFIG to FIP and specify the same to certtool 214$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 215 216 217ifeq (${SPD},spmd) 218ifneq ($(ARM_SPMC_MANIFEST_DTS),) 219FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 220endif 221endif 222 223include drivers/arm/ethosn/ethosn_npu.mk 224include plat/arm/board/common/board_common.mk 225include plat/arm/common/arm_common.mk 226include plat/arm/soc/common/soc_css.mk 227include plat/arm/css/common/css_common.mk 228