1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9USE_GIC_DRIVER := 2 10 11JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 12 plat/arm/common/arm_cci.c 13 14JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 15 plat/arm/board/juno/juno_security.c \ 16 plat/arm/board/juno/juno_trng.c \ 17 plat/arm/common/arm_tzc400.c 18 19ifneq (${ENABLE_STACK_PROTECTOR}, 0) 20JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 21endif 22 23# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 24# SCP during power management operations and for SCP RAM Firmware transfer. 25CSS_USE_SCMI_SDS_DRIVER := 1 26 27PLAT_INCLUDES := -Iplat/arm/board/juno/include 28 29PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 30 plat/arm/board/juno/juno_common.c 31 32# Flag to enable support for AArch32 state on JUNO 33JUNO_AARCH32_EL3_RUNTIME := 0 34$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 35$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 36 37# Flag to enable support for TZMP1 on JUNO 38JUNO_TZMP1 := 0 39$(eval $(call assert_boolean,JUNO_TZMP1)) 40ifeq (${JUNO_TZMP1}, 1) 41 ifeq (${ETHOSN_NPU_TZMP1},1) 42 $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1) 43 else 44 $(eval $(call add_define,JUNO_TZMP1)) 45 endif 46endif 47 48TRNG_SUPPORT := 1 49 50ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 51# Include BL32 in FIP 52NEED_BL32 := yes 53# BL31 is not required 54override BL31_SOURCES = 55 56# The BL32 needs to be built separately invoking the AARCH32 compiler and 57# be specifed via `BL32` build option. 58 ifneq (${ARCH}, aarch32) 59 override BL32_SOURCES = 60 endif 61else 62 ifeq (${ARCH}, aarch32) 63 $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32) 64 endif 65endif 66 67ifeq (${ARCH},aarch64) 68BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 69 lib/cpus/aarch64/cortex_a57.S \ 70 lib/cpus/aarch64/cortex_a72.S \ 71 plat/arm/board/juno/juno_err.c \ 72 plat/arm/board/juno/juno_bl1_setup.c \ 73 drivers/arm/sp805/sp805.c \ 74 ${JUNO_INTERCONNECT_SOURCES} \ 75 ${JUNO_SECURITY_SOURCES} 76 77BL2_SOURCES += drivers/arm/sp805/sp805.c \ 78 lib/utils/mem_region.c \ 79 plat/arm/board/juno/juno_err.c \ 80 plat/arm/board/juno/juno_bl2_setup.c \ 81 plat/arm/common/arm_nor_psci_mem_protect.c \ 82 ${JUNO_SECURITY_SOURCES} 83 84BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 85 86BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 87 lib/cpus/aarch64/cortex_a53.S \ 88 lib/cpus/aarch64/cortex_a57.S \ 89 lib/cpus/aarch64/cortex_a72.S \ 90 lib/utils/mem_region.c \ 91 lib/fconf/fconf.c \ 92 lib/fconf/fconf_dyn_cfg_getter.c \ 93 plat/arm/board/juno/juno_bl31_setup.c \ 94 plat/arm/board/juno/juno_pm.c \ 95 plat/arm/board/juno/juno_topology.c \ 96 plat/arm/common/arm_nor_psci_mem_protect.c \ 97 ${JUNO_INTERCONNECT_SOURCES} \ 98 ${JUNO_SECURITY_SOURCES} 99 100BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 101 102ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 103BL1_SOURCES += drivers/arm/css/sds/sds.c 104endif 105 106ifeq (${TRUSTED_BOARD_BOOT}, 1) 107 # Enable Juno specific TBBR images 108 $(eval $(call add_define,PLAT_TBBR_IMG_DEF)) 109 DTC_CPPFLAGS += ${PLAT_INCLUDES} 110 111 BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 112 BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 113 114 ifeq (${COT_DESC_IN_DTB},0) 115 BL2_SOURCES += plat/arm/board/juno/juno_tbbr_cot_bl2.c 116 endif 117endif 118 119endif 120 121ifneq (${RESET_TO_BL31},0) 122 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 123 Please set RESET_TO_BL31 to 0.") 124endif 125 126ifeq ($(USE_ROMLIB),1) 127all: $(BUILD_PLAT)/bl1_romlib.bin 128endif 129 130$(BUILD_PLAT)/bl1_romlib.bin: $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin 131 $(s)echo "Building combined BL1 and ROMLIB binary for Juno $@" 132 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 133 134# Errata workarounds for Cortex-A53: 135ERRATA_A53_819472 := 1 136ERRATA_A53_824069 := 1 137ERRATA_A53_826319 := 1 138ERRATA_A53_827319 := 1 139ERRATA_A53_835769 := 1 140ERRATA_A53_836870 := 1 141ERRATA_A53_843419 := 1 142ERRATA_A53_855873 := 1 143 144# Errata workarounds for Cortex-A57: 145ERRATA_A57_806969 := 0 146ERRATA_A57_813419 := 1 147ERRATA_A57_813420 := 1 148ERRATA_A57_814670 := 1 149ERRATA_A57_817169 := 1 150ERRATA_A57_826974 := 1 151ERRATA_A57_826977 := 1 152ERRATA_A57_828024 := 1 153ERRATA_A57_829520 := 1 154ERRATA_A57_833471 := 1 155ERRATA_A57_859972 := 0 156 157# Errata workarounds for Cortex-A72: 158ERRATA_A72_859971 := 0 159 160# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 161# power down sequence 162SKIP_A57_L1_FLUSH_PWR_DWN := 1 163 164# Do not enable SVE 165ENABLE_SVE_FOR_NS := 0 166 167# Enable the dynamic translation tables library. 168ifeq (${ARCH},aarch32) 169 ifeq (${RESET_TO_SP_MIN},1) 170 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 171 endif 172else 173 ifeq (${RESET_TO_BL31},1) 174 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 175 endif 176endif 177 178ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 179 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 180 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 181 else 182 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 183 endif 184endif 185 186BL1_CPPFLAGS += -march=armv8-a+crc 187BL2_CPPFLAGS += -march=armv8-a+crc 188BL2U_CPPFLAGS += -march=armv8-a+crc 189BL31_CPPFLAGS += -march=armv8-a+crc 190BL32_CPPFLAGS += -march=armv8-a+crc 191 192# Add the FDT_SOURCES and options for Dynamic Config 193FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 194 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \ 195 fdts/${PLAT}.dts 196 197FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 198TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 199HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 200 201# Add the FW_CONFIG to FIP and specify the same to certtool 202$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 203# Add the TB_FW_CONFIG to FIP and specify the same to certtool 204$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 205# Add the HW_CONFIG to FIP and specify the same to certtool 206$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 207 208include drivers/arm/ethosn/ethosn_npu.mk 209include plat/arm/board/common/board_common.mk 210include plat/arm/common/arm_common.mk 211include plat/arm/soc/common/soc_css.mk 212include plat/arm/css/common/css_common.mk 213