185135283SDan Handley# 2*c5c54e20SBoyan Karatotev# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 385135283SDan Handley# 482cb2c1aSdp-arm# SPDX-License-Identifier: BSD-3-Clause 585135283SDan Handley# 685135283SDan Handley 71fa05dabSChris Kayinclude common/fdt_wrappers.mk 81fa05dabSChris Kay 9*c5c54e20SBoyan KaratotevUSE_GIC_DRIVER := 2 1027573c59SAchin Gupta 116355f234SVikram KanigiriJUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 126355f234SVikram Kanigiri plat/arm/common/arm_cci.c 136355f234SVikram Kanigiri 1457f78201SSoby MathewJUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 15a9cc84d7SVikram Kanigiri plat/arm/board/juno/juno_security.c \ 16df9a39eaSdp-arm plat/arm/board/juno/juno_trng.c \ 17a9cc84d7SVikram Kanigiri plat/arm/common/arm_tzc400.c 18a9cc84d7SVikram Kanigiri 19e6d2aea1Sdp-armifneq (${ENABLE_STACK_PROTECTOR}, 0) 20e6d2aea1Sdp-armJUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 21e6d2aea1Sdp-armendif 226355f234SVikram Kanigiri 234da6f6cdSSathees Balya# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 244da6f6cdSSathees Balya# SCP during power management operations and for SCP RAM Firmware transfer. 254da6f6cdSSathees BalyaCSS_USE_SCMI_SDS_DRIVER := 1 264da6f6cdSSathees Balya 275932d194SAntonio Nino DiazPLAT_INCLUDES := -Iplat/arm/board/juno/include 2885135283SDan Handley 2958ea77a0SAntonio Nino DiazPLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 3058ea77a0SAntonio Nino Diaz plat/arm/board/juno/juno_common.c 3185135283SDan Handley 3207570d59SYatharth Kochar# Flag to enable support for AArch32 state on JUNO 3307570d59SYatharth KocharJUNO_AARCH32_EL3_RUNTIME := 0 3407570d59SYatharth Kochar$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 3507570d59SYatharth Kochar$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 3607570d59SYatharth Kochar 3760a23fd8SSummer Qin# Flag to enable support for TZMP1 on JUNO 3860a23fd8SSummer QinJUNO_TZMP1 := 0 3960a23fd8SSummer Qin$(eval $(call assert_boolean,JUNO_TZMP1)) 4060a23fd8SSummer Qinifeq (${JUNO_TZMP1}, 1) 41352366edSRajasekaran Kalidoss ifeq (${ETHOSN_NPU_TZMP1},1) 42352366edSRajasekaran Kalidoss $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1) 43035c9119SBjorn Engstrom else 4460a23fd8SSummer Qin $(eval $(call add_define,JUNO_TZMP1)) 4560a23fd8SSummer Qin endif 46035c9119SBjorn Engstromendif 4760a23fd8SSummer Qin 48cb5f0faaSAndre PrzywaraTRNG_SUPPORT := 1 49cb5f0faaSAndre Przywara 505744e874SSoby Mathewifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 515744e874SSoby Mathew# Include BL32 in FIP 525744e874SSoby MathewNEED_BL32 := yes 535744e874SSoby Mathew# BL31 is not required 545744e874SSoby Mathewoverride BL31_SOURCES = 555744e874SSoby Mathew 565744e874SSoby Mathew# The BL32 needs to be built separately invoking the AARCH32 compiler and 575744e874SSoby Mathew# be specifed via `BL32` build option. 585744e874SSoby Mathew ifneq (${ARCH}, aarch32) 595744e874SSoby Mathew override BL32_SOURCES = 605744e874SSoby Mathew endif 6175574864SJuan Pablo Condeelse 6275574864SJuan Pablo Conde ifeq (${ARCH}, aarch32) 6375574864SJuan Pablo Conde $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32) 6475574864SJuan Pablo Conde endif 655744e874SSoby Mathewendif 665744e874SSoby Mathew 6707570d59SYatharth Kocharifeq (${ARCH},aarch64) 6885135283SDan HandleyBL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 690f829ea9SBrendan Jackman lib/cpus/aarch64/cortex_a57.S \ 707b4c1405SJuan Castillo lib/cpus/aarch64/cortex_a72.S \ 714da6f6cdSSathees Balya plat/arm/board/juno/juno_err.c \ 72436223deSYatharth Kochar plat/arm/board/juno/juno_bl1_setup.c \ 73b0c97dafSAditya Angadi drivers/arm/sp805/sp805.c \ 74e6d2aea1Sdp-arm ${JUNO_INTERCONNECT_SOURCES} \ 75e6d2aea1Sdp-arm ${JUNO_SECURITY_SOURCES} 7685135283SDan Handley 7737b70031SAmbroise VincentBL2_SOURCES += drivers/arm/sp805/sp805.c \ 7837b70031SAmbroise Vincent lib/utils/mem_region.c \ 794da6f6cdSSathees Balya plat/arm/board/juno/juno_err.c \ 809d57a147SRoberto Vargas plat/arm/board/juno/juno_bl2_setup.c \ 819d57a147SRoberto Vargas plat/arm/common/arm_nor_psci_mem_protect.c \ 82a9cc84d7SVikram Kanigiri ${JUNO_SECURITY_SOURCES} 8385135283SDan Handley 84a9cc84d7SVikram KanigiriBL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 85dcda29f6SYatharth Kochar 86aa7877c4SAntonio Nino DiazBL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 87aa7877c4SAntonio Nino Diaz lib/cpus/aarch64/cortex_a53.S \ 88c1bb8a05SSoby Mathew lib/cpus/aarch64/cortex_a57.S \ 890f829ea9SBrendan Jackman lib/cpus/aarch64/cortex_a72.S \ 909d57a147SRoberto Vargas lib/utils/mem_region.c \ 915d5fb10fSMikael Olsson lib/fconf/fconf.c \ 925d5fb10fSMikael Olsson lib/fconf/fconf_dyn_cfg_getter.c \ 935d5fb10fSMikael Olsson plat/arm/board/juno/juno_bl31_setup.c \ 9489f2e589SChandni Cherukuri plat/arm/board/juno/juno_pm.c \ 950108047aSSoby Mathew plat/arm/board/juno/juno_topology.c \ 969d57a147SRoberto Vargas plat/arm/common/arm_nor_psci_mem_protect.c \ 976355f234SVikram Kanigiri ${JUNO_INTERCONNECT_SOURCES} \ 98a9cc84d7SVikram Kanigiri ${JUNO_SECURITY_SOURCES} 994da6f6cdSSathees Balya 1001fa05dabSChris KayBL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 1011fa05dabSChris Kay 1024da6f6cdSSathees Balyaifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 1035932d194SAntonio Nino DiazBL1_SOURCES += drivers/arm/css/sds/sds.c 1044da6f6cdSSathees Balyaendif 1054da6f6cdSSathees Balya 106a6ffddecSMax Shvetsovifeq (${TRUSTED_BOARD_BOOT}, 1) 10733bcaed1SRob Hughes # Enable Juno specific TBBR images 10833bcaed1SRob Hughes $(eval $(call add_define,PLAT_TBBR_IMG_DEF)) 10933bcaed1SRob Hughes DTC_CPPFLAGS += ${PLAT_INCLUDES} 11033bcaed1SRob Hughes 111a6ffddecSMax Shvetsov BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 112a6ffddecSMax Shvetsov BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 11333bcaed1SRob Hughes 11433bcaed1SRob Hughes ifeq (${COT_DESC_IN_DTB},0) 11533bcaed1SRob Hughes BL2_SOURCES += plat/arm/board/juno/juno_tbbr_cot_bl2.c 11633bcaed1SRob Hughes endif 117a6ffddecSMax Shvetsovendif 118a6ffddecSMax Shvetsov 11907570d59SYatharth Kocharendif 12085135283SDan Handley 12149d3a621SDeepak Pandeyifneq (${RESET_TO_BL31},0) 1229ce0d321SSandrine Bailleux $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 12349d3a621SDeepak Pandey Please set RESET_TO_BL31 to 0.") 12449d3a621SDeepak Pandeyendif 12549d3a621SDeepak Pandey 126afa5cfeaSSathees Balyaifeq ($(USE_ROMLIB),1) 1276e622818SChris Kayall: $(BUILD_PLAT)/bl1_romlib.bin 128afa5cfeaSSathees Balyaendif 129afa5cfeaSSathees Balya 1306e622818SChris Kay$(BUILD_PLAT)/bl1_romlib.bin: $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin 1317c4e1eeaSChris Kay $(s)echo "Building combined BL1 and ROMLIB binary for Juno $@" 132afa5cfeaSSathees Balya ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 133afa5cfeaSSathees Balya 13496ff2601SEleanor Bonnici# Errata workarounds for Cortex-A53: 135d6bf24dcSAmbroise VincentERRATA_A53_819472 := 1 136d6bf24dcSAmbroise VincentERRATA_A53_824069 := 1 13796ff2601SEleanor BonniciERRATA_A53_826319 := 1 138d6bf24dcSAmbroise VincentERRATA_A53_827319 := 1 139a94cc374SDouglas RaillardERRATA_A53_835769 := 1 14096ff2601SEleanor BonniciERRATA_A53_836870 := 1 141a94cc374SDouglas RaillardERRATA_A53_843419 := 1 142b75dc0e4SAndre PrzywaraERRATA_A53_855873 := 1 14396ff2601SEleanor Bonnici 14496ff2601SEleanor Bonnici# Errata workarounds for Cortex-A57: 14585135283SDan HandleyERRATA_A57_806969 := 0 146ccbec91cSAntonio Nino DiazERRATA_A57_813419 := 1 14785135283SDan HandleyERRATA_A57_813420 := 1 148d6bf24dcSAmbroise VincentERRATA_A57_814670 := 1 149d6bf24dcSAmbroise VincentERRATA_A57_817169 := 1 1506f822cccSDouglas RaillardERRATA_A57_826974 := 1 1516f822cccSDouglas RaillardERRATA_A57_826977 := 1 1526f822cccSDouglas RaillardERRATA_A57_828024 := 1 1536f822cccSDouglas RaillardERRATA_A57_829520 := 1 1546f822cccSDouglas RaillardERRATA_A57_833471 := 1 15596ff2601SEleanor BonniciERRATA_A57_859972 := 0 1566f822cccSDouglas Raillard 15796ff2601SEleanor Bonnici# Errata workarounds for Cortex-A72: 15896ff2601SEleanor BonniciERRATA_A72_859971 := 0 15985135283SDan Handley 16085135283SDan Handley# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 16185135283SDan Handley# power down sequence 16285135283SDan HandleySKIP_A57_L1_FLUSH_PWR_DWN := 1 16385135283SDan Handley 1643872fc2dSDavid Cunado# Do not enable SVE 1653872fc2dSDavid CunadoENABLE_SVE_FOR_NS := 0 1663872fc2dSDavid Cunado 1673661d8e7SAntonio Nino Diaz# Enable the dynamic translation tables library. 1683661d8e7SAntonio Nino Diazifeq (${ARCH},aarch32) 1693661d8e7SAntonio Nino Diaz ifeq (${RESET_TO_SP_MIN},1) 1701dc17569SMasahiro Yamada BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 1713661d8e7SAntonio Nino Diaz endif 1723661d8e7SAntonio Nino Diazelse 1733661d8e7SAntonio Nino Diaz ifeq (${RESET_TO_BL31},1) 1741dc17569SMasahiro Yamada BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 1753661d8e7SAntonio Nino Diaz endif 1763661d8e7SAntonio Nino Diazendif 1773661d8e7SAntonio Nino Diaz 17860e8f3cfSPetre-Ionut Tudorifeq (${ALLOW_RO_XLAT_TABLES}, 1) 17960e8f3cfSPetre-Ionut Tudor ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 1801dc17569SMasahiro Yamada BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 18160e8f3cfSPetre-Ionut Tudor else 1821dc17569SMasahiro Yamada BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 18360e8f3cfSPetre-Ionut Tudor endif 18460e8f3cfSPetre-Ionut Tudorendif 18560e8f3cfSPetre-Ionut Tudor 186eb18ce32SAndre PrzywaraBL1_CPPFLAGS += -march=armv8-a+crc 187eb18ce32SAndre PrzywaraBL2_CPPFLAGS += -march=armv8-a+crc 188eb18ce32SAndre PrzywaraBL2U_CPPFLAGS += -march=armv8-a+crc 189eb18ce32SAndre PrzywaraBL31_CPPFLAGS += -march=armv8-a+crc 190eb18ce32SAndre PrzywaraBL32_CPPFLAGS += -march=armv8-a+crc 191eb18ce32SAndre Przywara 1928075fc59SLouis Mayencourt# Add the FDT_SOURCES and options for Dynamic Config 1933cb84a54SManish V BadarkheFDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 1945d5fb10fSMikael Olsson plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \ 1955d5fb10fSMikael Olsson fdts/${PLAT}.dts 1968075fc59SLouis Mayencourt 1973cb84a54SManish V BadarkheFW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 1983cb84a54SManish V BadarkheTB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 1995d5fb10fSMikael OlssonHW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 2003cb84a54SManish V Badarkhe 2013cb84a54SManish V Badarkhe# Add the FW_CONFIG to FIP and specify the same to certtool 2023ab336a1SAnders Dellien$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 2038075fc59SLouis Mayencourt# Add the TB_FW_CONFIG to FIP and specify the same to certtool 2043ab336a1SAnders Dellien$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 2055d5fb10fSMikael Olsson# Add the HW_CONFIG to FIP and specify the same to certtool 2065d5fb10fSMikael Olsson$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 2078075fc59SLouis Mayencourt 208352366edSRajasekaran Kalidossinclude drivers/arm/ethosn/ethosn_npu.mk 20958ea77a0SAntonio Nino Diazinclude plat/arm/board/common/board_common.mk 21085135283SDan Handleyinclude plat/arm/common/arm_common.mk 21185135283SDan Handleyinclude plat/arm/soc/common/soc_css.mk 21285135283SDan Handleyinclude plat/arm/css/common/css_common.mk 213