1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __JUNO_TZMP1_DEF_H__ 8 #define __JUNO_TZMP1_DEF_H__ 9 10 #include <plat_arm.h> 11 12 /* 13 * Public memory regions for both protected and non-protected mode 14 * 15 * OPTEE shared memory 0xFEE00000 - 0xFEFFFFFF 16 */ 17 #define JUNO_AP_TZC_SHARE_DRAM1_SIZE ULL(0x02000000) 18 #define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 19 JUNO_AP_TZC_SHARE_DRAM1_SIZE) 20 #define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1) 21 22 /* ARM_MEDIA_FEATURES for MEDIA GPU Protect Mode Test */ 23 #define JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE 8 /* GPU/DPU protected, VPU outbuf */ 24 #define JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED 7 /* VPU protected */ 25 #define JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE 10 /* VPU private (firmware) */ 26 27 #define JUNO_VPU_TZC_PRIV_DRAM1_SIZE ULL(0x02000000) 28 #define JUNO_VPU_TZC_PRIV_DRAM1_BASE (JUNO_AP_TZC_SHARE_DRAM1_BASE - \ 29 JUNO_VPU_TZC_PRIV_DRAM1_SIZE) 30 #define JUNO_VPU_TZC_PRIV_DRAM1_END (JUNO_AP_TZC_SHARE_DRAM1_BASE - 1) 31 32 /* Video input protected buffer follows upper item */ 33 #define JUNO_VPU_TZC_PROT_DRAM1_SIZE ULL(0x06000000) 34 #define JUNO_VPU_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PRIV_DRAM1_BASE - \ 35 JUNO_VPU_TZC_PROT_DRAM1_SIZE) 36 #define JUNO_VPU_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PRIV_DRAM1_BASE - 1) 37 38 /* Video, graphics and display shares same NSAID and same protected buffer */ 39 #define JUNO_MEDIA_TZC_PROT_DRAM1_SIZE ULL(0x0e000000) 40 #define JUNO_MEDIA_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PROT_DRAM1_BASE - \ 41 JUNO_MEDIA_TZC_PROT_DRAM1_SIZE) 42 #define JUNO_MEDIA_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PROT_DRAM1_BASE - 1) 43 44 /* Rest of DRAM1 are Non-Secure public buffer */ 45 #define JUNO_NS_DRAM1_PT1_BASE ARM_DRAM1_BASE 46 #define JUNO_NS_DRAM1_PT1_END (JUNO_MEDIA_TZC_PROT_DRAM1_BASE - 1) 47 #define JUNO_NS_DRAM1_PT1_SIZE (JUNO_NS_DRAM1_PT1_END - \ 48 JUNO_NS_DRAM1_PT1_BASE + 1) 49 50 /* TZC filter flags */ 51 #define JUNO_MEDIA_TZC_NS_DEV_ACCESS (PLAT_ARM_TZC_NS_DEV_ACCESS | \ 52 TZC_REGION_ACCESS_RD(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE)) 53 54 /* VPU / GPU /DPU protected access */ 55 #define JUNO_MEDIA_TZC_PROT_ACCESS \ 56 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE) | \ 57 TZC_REGION_ACCESS_WR(TZC400_NSAID_AP)) 58 59 #define JUNO_VPU_TZC_PROT_ACCESS \ 60 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED)) 61 62 #define JUNO_VPU_TZC_PRIV_ACCESS \ 63 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE)) 64 65 /******************************************************************************* 66 * Mali-DP650 related constants 67 ******************************************************************************/ 68 /* Base address of DP650 */ 69 #define DP650_BASE 0x6f200000 70 /* offset to PROT_NSAID register */ 71 #define DP650_PROT_NSAID_OFFSET 0x10004 72 /* config to PROT_NSAID register */ 73 #define DP650_PROT_NSAID_CONFIG 0x08008888 74 75 /******************************************************************************* 76 * Mali-V550 related constants 77 ******************************************************************************/ 78 /* Base address of V550 */ 79 #define V550_BASE 0x6f030000 80 /* offset to PROTCTRL register */ 81 #define V550_PROTCTRL_OFFSET 0x0040 82 /* config to PROTCTRL register */ 83 #define V550_PROTCTRL_CONFIG 0xa8700000 84 85 #endif /* __JUNO_TZMP1_DEF_H__ */ 86