1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 8 #include <common/debug.h> 9 #include <drivers/arm/nic_400.h> 10 #include <lib/mmio.h> 11 #include <platform_def.h> 12 #include <plat/arm/common/plat_arm.h> 13 #include <plat/arm/soc/common/soc_css.h> 14 #include <plat/common/platform.h> 15 16 #include "juno_tzmp1_def.h" 17 18 #ifdef JUNO_TZMP1 19 /* 20 * Protect buffer for VPU/GPU/DPU memory usage with hardware protection 21 * enabled. Propose 224MB video output, 96 MB video input and 32MB video 22 * private. 23 * 24 * Ind Memory Range Caption S_ATTR NS_ATTR 25 * 1 0x080000000 - 0x0E7FFFFFF ARM_NS_DRAM1 NONE RDWR | MEDIA_RW 26 * 2 0x0E8000000 - 0x0F5FFFFFF JUNO_MEDIA_TZC_PROT_DRAM1 NONE MEDIA_RW | AP_WR 27 * 3 0x0F6000000 - 0x0FBFFFFFF JUNO_VPU_TZC_PROT_DRAM1 RDWR VPU_PROT_RW 28 * 4 0x0FC000000 - 0x0FDFFFFFF JUNO_VPU_TZC_PRIV_DRAM1 RDWR VPU_PRIV_RW 29 * 5 0x0FE000000 - 0x0FEFFFFFF JUNO_AP_TZC_SHARE_DRAM1 NONE RDWR | MEDIA_RW 30 * 6 0x0FF000000 - 0x0FFFFFFFF ARM_AP_TZC_DRAM1 RDWR NONE 31 * 7 0x880000000 - 0x9FFFFFFFF ARM_DRAM2 NONE RDWR | MEDIA_RW 32 * 33 * Memory regions are neighbored to save limited TZC regions. Calculation 34 * started from ARM_TZC_SHARE_DRAM1 since it is known and fixed for both 35 * protected-enabled and protected-disabled settings. 36 * 37 * Video private buffer aheads of ARM_TZC_SHARE_DRAM1 38 */ 39 40 static const arm_tzc_regions_info_t juno_tzmp1_tzc_regions[] = { 41 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0}, 42 {JUNO_NS_DRAM1_PT1_BASE, JUNO_NS_DRAM1_PT1_END, 43 TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS}, 44 {JUNO_MEDIA_TZC_PROT_DRAM1_BASE, JUNO_MEDIA_TZC_PROT_DRAM1_END, 45 TZC_REGION_S_NONE, JUNO_MEDIA_TZC_PROT_ACCESS}, 46 {JUNO_VPU_TZC_PROT_DRAM1_BASE, JUNO_VPU_TZC_PROT_DRAM1_END, 47 TZC_REGION_S_RDWR, JUNO_VPU_TZC_PROT_ACCESS}, 48 {JUNO_VPU_TZC_PRIV_DRAM1_BASE, JUNO_VPU_TZC_PRIV_DRAM1_END, 49 TZC_REGION_S_RDWR, JUNO_VPU_TZC_PRIV_ACCESS}, 50 {JUNO_AP_TZC_SHARE_DRAM1_BASE, JUNO_AP_TZC_SHARE_DRAM1_END, 51 TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS}, 52 {ARM_DRAM2_BASE, ARM_DRAM2_END, 53 TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS}, 54 {}, 55 }; 56 57 /******************************************************************************* 58 * Program dp650 to configure NSAID value for protected mode. 59 ******************************************************************************/ 60 static void init_dp650(void) 61 { 62 mmio_write_32(DP650_BASE + DP650_PROT_NSAID_OFFSET, 63 DP650_PROT_NSAID_CONFIG); 64 } 65 66 /******************************************************************************* 67 * Program v550 to configure NSAID value for protected mode. 68 ******************************************************************************/ 69 static void init_v550(void) 70 { 71 /* 72 * bits[31:28] is for PRIVATE, 73 * bits[27:24] is for OUTBUF, 74 * bits[23:20] is for PROTECTED. 75 */ 76 mmio_write_32(V550_BASE + V550_PROTCTRL_OFFSET, V550_PROTCTRL_CONFIG); 77 } 78 79 #endif /* JUNO_TZMP1 */ 80 81 /******************************************************************************* 82 * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs 83 * assigned to Non-Secure except some for the DMA-330. Assign those back to the 84 * Non-Secure world as well, otherwise EL1 may end up erroneously generating 85 * (untranslated) Secure transactions if it turns the SMMU on. 86 ******************************************************************************/ 87 static void init_mmu401(void) 88 { 89 uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET); 90 reg |= 0x1FF; 91 mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg); 92 } 93 94 /******************************************************************************* 95 * Program CSS-NIC400 to allow non-secure access to some CSS regions. 96 ******************************************************************************/ 97 static void css_init_nic400(void) 98 { 99 /* Note: This is the NIC-400 device on the CSS */ 100 mmio_write_32(PLAT_SOC_CSS_NIC400_BASE + 101 NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE), 102 ~0); 103 } 104 105 /******************************************************************************* 106 * Initialize debug configuration. 107 ******************************************************************************/ 108 static void init_debug_cfg(void) 109 { 110 #if !DEBUG 111 /* Set internal drive selection for SPIDEN. */ 112 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET, 113 1U << SPIDEN_SEL_SET_SHIFT); 114 115 /* Drive SPIDEN LOW to disable invasive debug of secure state. */ 116 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR, 117 1U << SPIDEN_INT_CLR_SHIFT); 118 #endif 119 } 120 121 /******************************************************************************* 122 * Initialize the secure environment. 123 ******************************************************************************/ 124 void plat_arm_security_setup(void) 125 { 126 /* Initialize debug configuration */ 127 init_debug_cfg(); 128 /* Initialize the TrustZone Controller */ 129 #ifdef JUNO_TZMP1 130 arm_tzc400_setup(PLAT_ARM_TZC_BASE, juno_tzmp1_tzc_regions); 131 INFO("TZC protected shared memory base address for TZMP usecase: %p\n", 132 (void *)JUNO_AP_TZC_SHARE_DRAM1_BASE); 133 INFO("TZC protected shared memory end address for TZMP usecase: %p\n", 134 (void *)JUNO_AP_TZC_SHARE_DRAM1_END); 135 #else 136 arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL); 137 #endif 138 /* Do ARM CSS internal NIC setup */ 139 css_init_nic400(); 140 /* Do ARM CSS SoC security setup */ 141 soc_css_security_setup(); 142 /* Initialize the SMMU SSD tables */ 143 init_mmu401(); 144 #ifdef JUNO_TZMP1 145 init_dp650(); 146 init_v550(); 147 #endif 148 } 149 150 #if TRUSTED_BOARD_BOOT 151 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 152 { 153 assert(heap_addr != NULL); 154 assert(heap_size != NULL); 155 156 return arm_get_mbedtls_heap(heap_addr, heap_size); 157 } 158 #endif 159