xref: /rk3399_ARM-atf/plat/arm/board/juno/juno_security.c (revision 23411d2c4adcec412befb4ffbbfbf81c743a59c6)
185135283SDan Handley /*
2*23411d2cSSummer Qin  * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
385135283SDan Handley  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
585135283SDan Handley  */
685135283SDan Handley 
785135283SDan Handley #include <mmio.h>
8883852caSVikram Kanigiri #include <nic_400.h>
985135283SDan Handley #include <plat_arm.h>
1085135283SDan Handley #include <soc_css.h>
1185135283SDan Handley #include "juno_def.h"
1285135283SDan Handley 
1385135283SDan Handley 
1485135283SDan Handley /*******************************************************************************
1585135283SDan Handley  * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
1685135283SDan Handley  * assigned to Non-Secure except some for the DMA-330. Assign those back to the
1785135283SDan Handley  * Non-Secure world as well, otherwise EL1 may end up erroneously generating
1885135283SDan Handley  * (untranslated) Secure transactions if it turns the SMMU on.
1985135283SDan Handley  ******************************************************************************/
2085135283SDan Handley static void init_mmu401(void)
2185135283SDan Handley {
2285135283SDan Handley 	uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
2385135283SDan Handley 	reg |= 0x1FF;
2485135283SDan Handley 	mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
2585135283SDan Handley }
2685135283SDan Handley 
2785135283SDan Handley /*******************************************************************************
28883852caSVikram Kanigiri  * Program CSS-NIC400 to allow non-secure access to some CSS regions.
29883852caSVikram Kanigiri  ******************************************************************************/
30883852caSVikram Kanigiri static void css_init_nic400(void)
31883852caSVikram Kanigiri {
32883852caSVikram Kanigiri 	/* Note: This is the NIC-400 device on the CSS */
33883852caSVikram Kanigiri 	mmio_write_32(PLAT_SOC_CSS_NIC400_BASE +
34883852caSVikram Kanigiri 		NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
35883852caSVikram Kanigiri 		~0);
36883852caSVikram Kanigiri }
37883852caSVikram Kanigiri 
38883852caSVikram Kanigiri /*******************************************************************************
3909fad498Sdp-arm  * Initialize debug configuration.
4009fad498Sdp-arm  ******************************************************************************/
4109fad498Sdp-arm static void init_debug_cfg(void)
4209fad498Sdp-arm {
4309fad498Sdp-arm #if !DEBUG
4409fad498Sdp-arm 	/* Set internal drive selection for SPIDEN. */
4509fad498Sdp-arm 	mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
4609fad498Sdp-arm 		1U << SPIDEN_SEL_SET_SHIFT);
4709fad498Sdp-arm 
4809fad498Sdp-arm 	/* Drive SPIDEN LOW to disable invasive debug of secure state. */
4909fad498Sdp-arm 	mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
5009fad498Sdp-arm 		1U << SPIDEN_INT_CLR_SHIFT);
5109fad498Sdp-arm #endif
5209fad498Sdp-arm }
5309fad498Sdp-arm 
5409fad498Sdp-arm /*******************************************************************************
5585135283SDan Handley  * Initialize the secure environment.
5685135283SDan Handley  ******************************************************************************/
5785135283SDan Handley void plat_arm_security_setup(void)
5885135283SDan Handley {
5909fad498Sdp-arm 	/* Initialize debug configuration */
6009fad498Sdp-arm 	init_debug_cfg();
6185135283SDan Handley 	/* Initialize the TrustZone Controller */
62*23411d2cSSummer Qin 	arm_tzc400_setup(NULL);
63883852caSVikram Kanigiri 	/* Do ARM CSS internal NIC setup */
64883852caSVikram Kanigiri 	css_init_nic400();
6585135283SDan Handley 	/* Do ARM CSS SoC security setup */
6685135283SDan Handley 	soc_css_security_setup();
6785135283SDan Handley 	/* Initialize the SMMU SSD tables */
6885135283SDan Handley 	init_mmu401();
6985135283SDan Handley }
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