1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef JUNO_DEF_H 8 #define JUNO_DEF_H 9 10 #include <utils_def.h> 11 12 /******************************************************************************* 13 * Juno memory map related constants 14 ******************************************************************************/ 15 16 /* Board revisions */ 17 #define REV_JUNO_R0 0x1 /* Rev B */ 18 #define REV_JUNO_R1 0x2 /* Rev C */ 19 #define REV_JUNO_R2 0x3 /* Rev D */ 20 21 /* Bypass offset from start of NOR flash */ 22 #define BL1_ROM_BYPASS_OFFSET 0x03EC0000 23 24 #define EMMC_BASE 0x0c000000 25 #define EMMC_SIZE 0x04000000 26 27 #define PSRAM_BASE 0x14000000 28 #define PSRAM_SIZE 0x02000000 29 30 #define JUNO_SSC_VER_PART_NUM 0x030 31 32 /******************************************************************************* 33 * Juno topology related constants 34 ******************************************************************************/ 35 #define JUNO_CLUSTER_COUNT 2 36 #define JUNO_CLUSTER0_CORE_COUNT 2 37 #define JUNO_CLUSTER1_CORE_COUNT 4 38 39 /******************************************************************************* 40 * TZC-400 related constants 41 ******************************************************************************/ 42 #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ 43 #define TZC400_NSAID_PCIE 1 44 #define TZC400_NSAID_HDLCD0 2 45 #define TZC400_NSAID_HDLCD1 3 46 #define TZC400_NSAID_USB 4 47 #define TZC400_NSAID_DMA330 5 48 #define TZC400_NSAID_THINLINKS 6 49 #define TZC400_NSAID_AP 9 50 #define TZC400_NSAID_GPU 10 51 #define TZC400_NSAID_SCP 11 52 #define TZC400_NSAID_CORESIGHT 12 53 54 /******************************************************************************* 55 * TRNG related constants 56 ******************************************************************************/ 57 #define TRNG_BASE 0x7FE60000ULL 58 #define TRNG_NOUTPUTS 4 59 #define TRNG_STATUS 0x10 60 #define TRNG_INTMASK 0x14 61 #define TRNG_CONFIG 0x18 62 #define TRNG_CONTROL 0x1C 63 #define TRNG_NBYTES 16 /* Number of bytes generated per round. */ 64 65 /******************************************************************************* 66 * MMU-401 related constants 67 ******************************************************************************/ 68 #define MMU401_SSD_OFFSET 0x4000 69 #define MMU401_DMA330_BASE 0x7fb00000 70 71 /******************************************************************************* 72 * Interrupt handling constants 73 ******************************************************************************/ 74 #define JUNO_IRQ_DMA_SMMU 126 75 #define JUNO_IRQ_HDLCD0_SMMU 128 76 #define JUNO_IRQ_HDLCD1_SMMU 130 77 #define JUNO_IRQ_USB_SMMU 132 78 #define JUNO_IRQ_THIN_LINKS_SMMU 134 79 #define JUNO_IRQ_SEC_I2C 137 80 #define JUNO_IRQ_GPU_SMMU_1 73 81 #define JUNO_IRQ_ETR_SMMU 75 82 83 /******************************************************************************* 84 * Memprotect definitions 85 ******************************************************************************/ 86 /* PSCI memory protect definitions: 87 * This variable is stored in a non-secure flash because some ARM reference 88 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 89 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 90 */ 91 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 92 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 93 94 #endif /* JUNO_DEF_H */ 95