185135283SDan Handley /* 2df9a39eaSdp-arm * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 385135283SDan Handley * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 585135283SDan Handley */ 685135283SDan Handley 785135283SDan Handley #ifndef __JUNO_DEF_H__ 885135283SDan Handley #define __JUNO_DEF_H__ 985135283SDan Handley 1085135283SDan Handley 1185135283SDan Handley /******************************************************************************* 1285135283SDan Handley * Juno memory map related constants 1385135283SDan Handley ******************************************************************************/ 1485135283SDan Handley 1585135283SDan Handley /* Board revisions */ 1685135283SDan Handley #define REV_JUNO_R0 0x1 /* Rev B */ 1785135283SDan Handley #define REV_JUNO_R1 0x2 /* Rev C */ 1823d39dbcSSandrine Bailleux #define REV_JUNO_R2 0x3 /* Rev D */ 1985135283SDan Handley 2085135283SDan Handley /* Bypass offset from start of NOR flash */ 2185135283SDan Handley #define BL1_ROM_BYPASS_OFFSET 0x03EC0000 2285135283SDan Handley 2385135283SDan Handley #define EMMC_BASE 0x0c000000 2485135283SDan Handley #define EMMC_SIZE 0x04000000 2585135283SDan Handley 2685135283SDan Handley #define PSRAM_BASE 0x14000000 2785135283SDan Handley #define PSRAM_SIZE 0x02000000 2885135283SDan Handley 29421295a0SVikram Kanigiri #define JUNO_SSC_VER_PART_NUM 0x030 3085135283SDan Handley 3185135283SDan Handley /******************************************************************************* 320108047aSSoby Mathew * Juno topology related constants 330108047aSSoby Mathew ******************************************************************************/ 340108047aSSoby Mathew #define JUNO_CLUSTER_COUNT 2 350108047aSSoby Mathew #define JUNO_CLUSTER0_CORE_COUNT 2 360108047aSSoby Mathew #define JUNO_CLUSTER1_CORE_COUNT 4 370108047aSSoby Mathew 380108047aSSoby Mathew /******************************************************************************* 3985135283SDan Handley * TZC-400 related constants 4085135283SDan Handley ******************************************************************************/ 4185135283SDan Handley #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ 4285135283SDan Handley #define TZC400_NSAID_PCIE 1 4385135283SDan Handley #define TZC400_NSAID_HDLCD0 2 4485135283SDan Handley #define TZC400_NSAID_HDLCD1 3 4585135283SDan Handley #define TZC400_NSAID_USB 4 4685135283SDan Handley #define TZC400_NSAID_DMA330 5 4785135283SDan Handley #define TZC400_NSAID_THINLINKS 6 4885135283SDan Handley #define TZC400_NSAID_AP 9 4985135283SDan Handley #define TZC400_NSAID_GPU 10 5085135283SDan Handley #define TZC400_NSAID_SCP 11 5185135283SDan Handley #define TZC400_NSAID_CORESIGHT 12 5285135283SDan Handley 5385135283SDan Handley /******************************************************************************* 54df9a39eaSdp-arm * TRNG related constants 55df9a39eaSdp-arm ******************************************************************************/ 56df9a39eaSdp-arm #define TRNG_BASE 0x7FE60000ULL 57df9a39eaSdp-arm #define TRNG_NOUTPUTS 4 58df9a39eaSdp-arm #define TRNG_STATUS 0x10 59df9a39eaSdp-arm #define TRNG_INTMASK 0x14 60df9a39eaSdp-arm #define TRNG_CONFIG 0x18 61df9a39eaSdp-arm #define TRNG_CONTROL 0x1C 62e6d2aea1Sdp-arm #define TRNG_NBYTES 16 /* Number of bytes generated per round. */ 63df9a39eaSdp-arm 64df9a39eaSdp-arm /******************************************************************************* 6585135283SDan Handley * MMU-401 related constants 6685135283SDan Handley ******************************************************************************/ 6785135283SDan Handley #define MMU401_SSD_OFFSET 0x4000 6885135283SDan Handley #define MMU401_DMA330_BASE 0x7fb00000 6985135283SDan Handley 70a7270d35SVikram Kanigiri /******************************************************************************* 71a7270d35SVikram Kanigiri * Interrupt handling constants 72a7270d35SVikram Kanigiri ******************************************************************************/ 73a7270d35SVikram Kanigiri #define JUNO_IRQ_DMA_SMMU 126 74a7270d35SVikram Kanigiri #define JUNO_IRQ_HDLCD0_SMMU 128 75a7270d35SVikram Kanigiri #define JUNO_IRQ_HDLCD1_SMMU 130 76a7270d35SVikram Kanigiri #define JUNO_IRQ_USB_SMMU 132 77a7270d35SVikram Kanigiri #define JUNO_IRQ_THIN_LINKS_SMMU 134 78a7270d35SVikram Kanigiri #define JUNO_IRQ_SEC_I2C 137 79a7270d35SVikram Kanigiri #define JUNO_IRQ_GPU_SMMU_1 73 80a7270d35SVikram Kanigiri #define JUNO_IRQ_ETR_SMMU 75 8185135283SDan Handley 8285135283SDan Handley #endif /* __JUNO_DEF_H__ */ 83