185135283SDan Handley /* 2*1083b2b3SAntonio Nino Diaz * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 385135283SDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 585135283SDan Handley */ 685135283SDan Handley 7*1083b2b3SAntonio Nino Diaz #ifndef JUNO_DEF_H 8*1083b2b3SAntonio Nino Diaz #define JUNO_DEF_H 985135283SDan Handley 10*1083b2b3SAntonio Nino Diaz #include <utils_def.h> 1185135283SDan Handley 1285135283SDan Handley /******************************************************************************* 1385135283SDan Handley * Juno memory map related constants 1485135283SDan Handley ******************************************************************************/ 1585135283SDan Handley 1685135283SDan Handley /* Board revisions */ 1785135283SDan Handley #define REV_JUNO_R0 0x1 /* Rev B */ 1885135283SDan Handley #define REV_JUNO_R1 0x2 /* Rev C */ 1923d39dbcSSandrine Bailleux #define REV_JUNO_R2 0x3 /* Rev D */ 2085135283SDan Handley 2185135283SDan Handley /* Bypass offset from start of NOR flash */ 2285135283SDan Handley #define BL1_ROM_BYPASS_OFFSET 0x03EC0000 2385135283SDan Handley 2485135283SDan Handley #define EMMC_BASE 0x0c000000 2585135283SDan Handley #define EMMC_SIZE 0x04000000 2685135283SDan Handley 2785135283SDan Handley #define PSRAM_BASE 0x14000000 2885135283SDan Handley #define PSRAM_SIZE 0x02000000 2985135283SDan Handley 30421295a0SVikram Kanigiri #define JUNO_SSC_VER_PART_NUM 0x030 3185135283SDan Handley 3285135283SDan Handley /******************************************************************************* 330108047aSSoby Mathew * Juno topology related constants 340108047aSSoby Mathew ******************************************************************************/ 350108047aSSoby Mathew #define JUNO_CLUSTER_COUNT 2 360108047aSSoby Mathew #define JUNO_CLUSTER0_CORE_COUNT 2 370108047aSSoby Mathew #define JUNO_CLUSTER1_CORE_COUNT 4 380108047aSSoby Mathew 390108047aSSoby Mathew /******************************************************************************* 4085135283SDan Handley * TZC-400 related constants 4185135283SDan Handley ******************************************************************************/ 4285135283SDan Handley #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ 4385135283SDan Handley #define TZC400_NSAID_PCIE 1 4485135283SDan Handley #define TZC400_NSAID_HDLCD0 2 4585135283SDan Handley #define TZC400_NSAID_HDLCD1 3 4685135283SDan Handley #define TZC400_NSAID_USB 4 4785135283SDan Handley #define TZC400_NSAID_DMA330 5 4885135283SDan Handley #define TZC400_NSAID_THINLINKS 6 4985135283SDan Handley #define TZC400_NSAID_AP 9 5085135283SDan Handley #define TZC400_NSAID_GPU 10 5185135283SDan Handley #define TZC400_NSAID_SCP 11 5285135283SDan Handley #define TZC400_NSAID_CORESIGHT 12 5385135283SDan Handley 5485135283SDan Handley /******************************************************************************* 55df9a39eaSdp-arm * TRNG related constants 56df9a39eaSdp-arm ******************************************************************************/ 57df9a39eaSdp-arm #define TRNG_BASE 0x7FE60000ULL 58df9a39eaSdp-arm #define TRNG_NOUTPUTS 4 59df9a39eaSdp-arm #define TRNG_STATUS 0x10 60df9a39eaSdp-arm #define TRNG_INTMASK 0x14 61df9a39eaSdp-arm #define TRNG_CONFIG 0x18 62df9a39eaSdp-arm #define TRNG_CONTROL 0x1C 63e6d2aea1Sdp-arm #define TRNG_NBYTES 16 /* Number of bytes generated per round. */ 64df9a39eaSdp-arm 65df9a39eaSdp-arm /******************************************************************************* 6685135283SDan Handley * MMU-401 related constants 6785135283SDan Handley ******************************************************************************/ 6885135283SDan Handley #define MMU401_SSD_OFFSET 0x4000 6985135283SDan Handley #define MMU401_DMA330_BASE 0x7fb00000 7085135283SDan Handley 71a7270d35SVikram Kanigiri /******************************************************************************* 72a7270d35SVikram Kanigiri * Interrupt handling constants 73a7270d35SVikram Kanigiri ******************************************************************************/ 74a7270d35SVikram Kanigiri #define JUNO_IRQ_DMA_SMMU 126 75a7270d35SVikram Kanigiri #define JUNO_IRQ_HDLCD0_SMMU 128 76a7270d35SVikram Kanigiri #define JUNO_IRQ_HDLCD1_SMMU 130 77a7270d35SVikram Kanigiri #define JUNO_IRQ_USB_SMMU 132 78a7270d35SVikram Kanigiri #define JUNO_IRQ_THIN_LINKS_SMMU 134 79a7270d35SVikram Kanigiri #define JUNO_IRQ_SEC_I2C 137 80a7270d35SVikram Kanigiri #define JUNO_IRQ_GPU_SMMU_1 73 81a7270d35SVikram Kanigiri #define JUNO_IRQ_ETR_SMMU 75 8285135283SDan Handley 83e237c1baSRoberto Vargas /******************************************************************************* 84e237c1baSRoberto Vargas * Memprotect definitions 85e237c1baSRoberto Vargas ******************************************************************************/ 86e237c1baSRoberto Vargas /* PSCI memory protect definitions: 87e237c1baSRoberto Vargas * This variable is stored in a non-secure flash because some ARM reference 88e237c1baSRoberto Vargas * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 89e237c1baSRoberto Vargas * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 90e237c1baSRoberto Vargas */ 91e237c1baSRoberto Vargas #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 92e237c1baSRoberto Vargas V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 93e237c1baSRoberto Vargas 94*1083b2b3SAntonio Nino Diaz #endif /* JUNO_DEF_H */ 95