1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/smccc.h> 8 #include <platform_def.h> 9 #include <services/arm_arch_svc.h> 10 11 #include <plat/arm/common/plat_arm.h> 12 13 /* 14 * Table of memory regions for different BL stages to map using the MMU. 15 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 16 * of mapping it. 17 */ 18 #ifdef IMAGE_BL1 19 const mmap_region_t plat_arm_mmap[] = { 20 ARM_MAP_SHARED_RAM, 21 V2M_MAP_FLASH0_RW, 22 V2M_MAP_IOFPGA, 23 CSS_MAP_DEVICE, 24 SOC_CSS_MAP_DEVICE, 25 #if TRUSTED_BOARD_BOOT 26 /* Map DRAM to authenticate NS_BL2U image. */ 27 ARM_MAP_NS_DRAM1, 28 #endif 29 {0} 30 }; 31 #endif 32 #ifdef IMAGE_BL2 33 const mmap_region_t plat_arm_mmap[] = { 34 ARM_MAP_SHARED_RAM, 35 V2M_MAP_FLASH0_RW, 36 #ifdef PLAT_ARM_MEM_PROT_ADDR 37 ARM_V2M_MAP_MEM_PROTECT, 38 #endif 39 V2M_MAP_IOFPGA, 40 CSS_MAP_DEVICE, 41 SOC_CSS_MAP_DEVICE, 42 ARM_MAP_NS_DRAM1, 43 #ifdef __aarch64__ 44 ARM_MAP_DRAM2, 45 #endif 46 #ifdef SPD_tspd 47 ARM_MAP_TSP_SEC_MEM, 48 #endif 49 #ifdef SPD_opteed 50 ARM_MAP_OPTEE_CORE_MEM, 51 ARM_OPTEE_PAGEABLE_LOAD_MEM, 52 #endif 53 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 54 ARM_MAP_BL1_RW, 55 #endif 56 #ifdef JUNO_ETHOSN_TZMP1 57 JUNO_ETHOSN_PROT_FW_RW, 58 #endif 59 {0} 60 }; 61 #endif 62 #ifdef IMAGE_BL2U 63 const mmap_region_t plat_arm_mmap[] = { 64 ARM_MAP_SHARED_RAM, 65 CSS_MAP_DEVICE, 66 CSS_MAP_SCP_BL2U, 67 V2M_MAP_IOFPGA, 68 SOC_CSS_MAP_DEVICE, 69 {0} 70 }; 71 #endif 72 #ifdef IMAGE_BL31 73 const mmap_region_t plat_arm_mmap[] = { 74 ARM_MAP_SHARED_RAM, 75 V2M_MAP_IOFPGA, 76 CSS_MAP_DEVICE, 77 #ifdef PLAT_ARM_MEM_PROT_ADDR 78 ARM_V2M_MAP_MEM_PROTECT, 79 #endif 80 SOC_CSS_MAP_DEVICE, 81 ARM_DTB_DRAM_NS, 82 #ifdef JUNO_ETHOSN_TZMP1 83 JUNO_ETHOSN_PROT_FW_RO, 84 #endif 85 {0} 86 }; 87 #endif 88 #ifdef IMAGE_BL32 89 const mmap_region_t plat_arm_mmap[] = { 90 #ifndef __aarch64__ 91 ARM_MAP_SHARED_RAM, 92 #ifdef PLAT_ARM_MEM_PROT_ADDR 93 ARM_V2M_MAP_MEM_PROTECT, 94 #endif 95 #endif 96 V2M_MAP_IOFPGA, 97 CSS_MAP_DEVICE, 98 SOC_CSS_MAP_DEVICE, 99 {0} 100 }; 101 #endif 102 103 ARM_CASSERT_MMAP 104 105 /***************************************************************************** 106 * plat_is_smccc_feature_available() - This function checks whether SMCCC 107 * feature is availabile for platform. 108 * @fid: SMCCC function id 109 * 110 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 111 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 112 *****************************************************************************/ 113 int32_t plat_is_smccc_feature_available(u_register_t fid) 114 { 115 switch (fid) { 116 case SMCCC_ARCH_SOC_ID: 117 return SMC_ARCH_CALL_SUCCESS; 118 default: 119 return SMC_ARCH_CALL_NOT_SUPPORTED; 120 } 121 } 122 123 /* Get SOC version */ 124 int32_t plat_get_soc_version(void) 125 { 126 return (int32_t) 127 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, 128 ARM_SOC_IDENTIFICATION_CODE) | 129 (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK)); 130 } 131 132 /* Get SOC revision */ 133 int32_t plat_get_soc_revision(void) 134 { 135 unsigned int sys_id; 136 137 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 138 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & 139 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); 140 } 141