1 /* 2 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <lib/fconf/fconf.h> 11 #include <lib/fconf/fconf_dyn_cfg_getter.h> 12 13 #include <plat/arm/common/plat_arm.h> 14 15 void __init bl31_early_platform_setup2(u_register_t arg0, 16 u_register_t arg1, u_register_t arg2, u_register_t arg3) 17 { 18 const struct dyn_cfg_dtb_info_t *soc_fw_config_info; 19 20 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); 21 22 /* Fill the properties struct with the info from the config dtb */ 23 fconf_populate("FW_CONFIG", arg1); 24 25 soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); 26 if (soc_fw_config_info != NULL) { 27 arg1 = soc_fw_config_info->config_addr; 28 } 29 30 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 31 32 /* 33 * Initialize Interconnect for this cluster during cold boot. 34 * No need for locks as no other CPU is active. 35 */ 36 plat_arm_interconnect_init(); 37 38 /* 39 * Enable Interconnect coherency for the primary CPU's cluster. 40 * Earlier bootloader stages might already do this (e.g. Trusted 41 * Firmware's BL1 does it) but we can't assume so. There is no harm in 42 * executing this code twice anyway. 43 * Platform specific PSCI code will enable coherency for other 44 * clusters. 45 */ 46 plat_arm_interconnect_enter_coherency(); 47 } 48 49 void __init bl31_plat_arch_setup(void) 50 { 51 arm_bl31_plat_arch_setup(); 52 53 /* HW_CONFIG was also loaded by BL2 */ 54 const struct dyn_cfg_dtb_info_t *hw_config_info; 55 56 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 57 assert(hw_config_info != NULL); 58 59 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 60 } 61