1*5d5fb10fSMikael Olsson /* 2*5d5fb10fSMikael Olsson * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3*5d5fb10fSMikael Olsson * 4*5d5fb10fSMikael Olsson * SPDX-License-Identifier: BSD-3-Clause 5*5d5fb10fSMikael Olsson */ 6*5d5fb10fSMikael Olsson 7*5d5fb10fSMikael Olsson #include <assert.h> 8*5d5fb10fSMikael Olsson 9*5d5fb10fSMikael Olsson #include <common/debug.h> 10*5d5fb10fSMikael Olsson #include <lib/fconf/fconf.h> 11*5d5fb10fSMikael Olsson #include <lib/fconf/fconf_dyn_cfg_getter.h> 12*5d5fb10fSMikael Olsson 13*5d5fb10fSMikael Olsson #include <plat/arm/common/plat_arm.h> 14*5d5fb10fSMikael Olsson 15*5d5fb10fSMikael Olsson void __init bl31_early_platform_setup2(u_register_t arg0, 16*5d5fb10fSMikael Olsson u_register_t arg1, u_register_t arg2, u_register_t arg3) 17*5d5fb10fSMikael Olsson { 18*5d5fb10fSMikael Olsson const struct dyn_cfg_dtb_info_t *soc_fw_config_info; 19*5d5fb10fSMikael Olsson 20*5d5fb10fSMikael Olsson INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); 21*5d5fb10fSMikael Olsson 22*5d5fb10fSMikael Olsson /* Fill the properties struct with the info from the config dtb */ 23*5d5fb10fSMikael Olsson fconf_populate("FW_CONFIG", arg1); 24*5d5fb10fSMikael Olsson 25*5d5fb10fSMikael Olsson soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); 26*5d5fb10fSMikael Olsson if (soc_fw_config_info != NULL) { 27*5d5fb10fSMikael Olsson arg1 = soc_fw_config_info->config_addr; 28*5d5fb10fSMikael Olsson } 29*5d5fb10fSMikael Olsson 30*5d5fb10fSMikael Olsson arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 31*5d5fb10fSMikael Olsson 32*5d5fb10fSMikael Olsson /* 33*5d5fb10fSMikael Olsson * Initialize Interconnect for this cluster during cold boot. 34*5d5fb10fSMikael Olsson * No need for locks as no other CPU is active. 35*5d5fb10fSMikael Olsson */ 36*5d5fb10fSMikael Olsson plat_arm_interconnect_init(); 37*5d5fb10fSMikael Olsson 38*5d5fb10fSMikael Olsson /* 39*5d5fb10fSMikael Olsson * Enable Interconnect coherency for the primary CPU's cluster. 40*5d5fb10fSMikael Olsson * Earlier bootloader stages might already do this (e.g. Trusted 41*5d5fb10fSMikael Olsson * Firmware's BL1 does it) but we can't assume so. There is no harm in 42*5d5fb10fSMikael Olsson * executing this code twice anyway. 43*5d5fb10fSMikael Olsson * Platform specific PSCI code will enable coherency for other 44*5d5fb10fSMikael Olsson * clusters. 45*5d5fb10fSMikael Olsson */ 46*5d5fb10fSMikael Olsson plat_arm_interconnect_enter_coherency(); 47*5d5fb10fSMikael Olsson } 48*5d5fb10fSMikael Olsson 49*5d5fb10fSMikael Olsson void __init bl31_plat_arch_setup(void) 50*5d5fb10fSMikael Olsson { 51*5d5fb10fSMikael Olsson arm_bl31_plat_arch_setup(); 52*5d5fb10fSMikael Olsson 53*5d5fb10fSMikael Olsson /* HW_CONFIG was also loaded by BL2 */ 54*5d5fb10fSMikael Olsson const struct dyn_cfg_dtb_info_t *hw_config_info; 55*5d5fb10fSMikael Olsson 56*5d5fb10fSMikael Olsson hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 57*5d5fb10fSMikael Olsson assert(hw_config_info != NULL); 58*5d5fb10fSMikael Olsson 59*5d5fb10fSMikael Olsson fconf_populate("HW_CONFIG", hw_config_info->config_addr); 60*5d5fb10fSMikael Olsson } 61