1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/bl_common.h> 10 #include <common/debug.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/css/sds.h> 13 #include <drivers/arm/sp805.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/arm/common/arm_def.h> 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 void juno_reset_to_aarch32_state(void); 20 21 static int is_watchdog_reset(void) 22 { 23 #if !CSS_USE_SCMI_SDS_DRIVER 24 #define RESET_REASON_WDOG_RESET (0x2) 25 const uint32_t *reset_flags_ptr = (const uint32_t *)SSC_GPRETN; 26 27 if ((*reset_flags_ptr & RESET_REASON_WDOG_RESET) != 0) 28 return 1; 29 30 return 0; 31 #else 32 int ret; 33 uint32_t scp_reset_synd_flags; 34 35 ret = sds_init(SDS_SCP_AP_REGION_ID); 36 if (ret != SDS_OK) { 37 ERROR("SCP SDS initialization failed\n"); 38 panic(); 39 } 40 41 ret = sds_struct_read(SDS_SCP_AP_REGION_ID, 42 SDS_RESET_SYNDROME_STRUCT_ID, 43 SDS_RESET_SYNDROME_OFFSET, 44 &scp_reset_synd_flags, 45 SDS_RESET_SYNDROME_SIZE, 46 SDS_ACCESS_MODE_NON_CACHED); 47 if (ret != SDS_OK) { 48 ERROR("Getting reset reason from SDS failed\n"); 49 panic(); 50 } 51 52 /* Check if the WATCHDOG_RESET_BIT is set in the reset syndrome */ 53 if (scp_reset_synd_flags & SDS_RESET_SYNDROME_AP_WD_RESET_BIT) 54 return 1; 55 56 return 0; 57 #endif 58 } 59 60 /******************************************************************************* 61 * The following function checks if Firmware update is needed, 62 * by checking if TOC in FIP image is valid or watchdog reset happened. 63 ******************************************************************************/ 64 bool plat_arm_bl1_fwu_needed(void) 65 { 66 int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR); 67 68 /* Check if TOC is invalid or watchdog reset happened. */ 69 return (!arm_io_is_toc_valid() || (((nv_flags == -EAUTH) || 70 (nv_flags == -ENOENT)) && is_watchdog_reset())); 71 } 72 73 /******************************************************************************* 74 * On JUNO update the arg2 with address of SCP_BL2U image info. 75 ******************************************************************************/ 76 void bl1_plat_set_ep_info(unsigned int image_id, 77 entry_point_info_t *ep_info) 78 { 79 if (image_id == BL2U_IMAGE_ID) { 80 image_desc_t *image_desc = bl1_plat_get_image_desc(SCP_BL2U_IMAGE_ID); 81 ep_info->args.arg2 = (unsigned long)&image_desc->image_info; 82 } 83 } 84 85 /******************************************************************************* 86 * On Juno clear SYS_NVFLAGS and wait for watchdog reset. 87 ******************************************************************************/ 88 __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) 89 { 90 uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR); 91 92 /* Clear the NV flags register. */ 93 mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR), 94 nv_flags); 95 96 /* Setup the watchdog to reset the system as soon as possible */ 97 sp805_refresh(ARM_SP805_TWDG_BASE, 1U); 98 99 while (true) 100 wfi(); 101 } 102 103 #if JUNO_AARCH32_EL3_RUNTIME 104 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 105 { 106 #if !ARM_DISABLE_TRUSTED_WDOG 107 /* Disable watchdog before leaving BL1 */ 108 sp805_stop(ARM_SP805_TWDG_BASE); 109 #endif 110 111 juno_reset_to_aarch32_state(); 112 } 113 #endif /* JUNO_AARCH32_EL3_RUNTIME */ 114 115 void plat_arm_secure_wdt_start(void) 116 { 117 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 118 } 119 120 void plat_arm_secure_wdt_stop(void) 121 { 122 sp805_stop(ARM_SP805_TWDG_BASE); 123 } 124